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| Number | Title | Issue Date |
| 5577214 | Programmable hold delay An EISA-compatible computer system having an arbitration mechanism which incorporates a programmable hold delay register and counter for delaying a CPU hold request (DHOLD) by a programmable number of BCLK cycles after an EISA device wins the top level an... | 11/19/1996 |
| 5574921 | Method and apparatus for reducing bus noise and power consumption In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the... | 11/12/1996 |
| 5572736 | Method and apparatus for reducing bus noise and power consumption In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the... | 11/05/1996 |
| 5572685 | Computer system A computer system has a backplane including a SCSI (small computer system interface) bus for connecting a host processor to a number of disk drive units. The bus operates in a conventional manner to set up a connection, until the stage where the initiator... | 11/05/1996 |
| 5553240 | Determining a winner of a race in a data processing system A first peer entity in a data processing system comprising a plurality of similar peer entities searches for a share control file for a system privilege. The share control file contains an address of a master entity which controls the system privilege. Th... | 09/03/1996 |
| 5535395 | Prioritization of microprocessors in multiprocessor computer systems Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization sche... | 07/09/1996 |
| 5519871 | Data save apparatus for a battery-powered data processing unit A data save apparatus for a data processing unit including at least volatile storage and a battery housed in the data processing unit to supply power thereto, the data save apparatus predicts that the battery is about to be removed from the data processin... | 05/21/1996 |
| 5517624 | Multiplexed communication protocol between central and distributed peripherals in multiprocessor computer systems A multiplexed communication protocol for broadcasting interrupt, DMA and other miscellaneous data across a bus from a central peripheral device to a plurality of distributed peripheral devices associated with each processor in a multiprocessor computer sy... | 05/14/1996 |
| 5513326 | System for optimizing data transfer Optimizing data transfer to a storage device by providing a speed control circuit which adjusts, in a continuously varying manner, a transfer rate of a storage device according to utilization of a data buffer.... | 04/30/1996 |
| 5506990 | Key lock system for personal computer A system for controlling the operation of computer power and reset switches. A separate key switch enables a user to selectively disable the power and reset switches of the computer. The user has the option of operating the computer in a secured mode, in ... | 04/09/1996 |
| 5502821 | Method of determining devices requesting the transfer of data signals on a bus A method is described for determining readiness of devices in a digital data bus system to transfer data signals. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lin... | 03/26/1996 |
| 5499345 | Bus arbitration system A bus arbitration system for a data processing apparatus to which a plurality of bus masters are connected. The counter section counts the duration of bus occupation of the bus masters. The arbitrating section of the apparatus monitors whether the bus is ... | 03/12/1996 |
| 5499374 | Event driven communication network A cost-effective motion control system communication architecture is provided that supports a centralized control node, distributed control nodes, and smart I/O peripheral control nodes. Networks designed using this architecture, which employs a serial bu... | 03/12/1996 |
| 5495586 | Computer system having memory card/disk storage unit used as external storage device In a computer system using either a memory card or a hard-disk drive (HDD) as an external storage device, a slot formed in a computer body for insertion of the external storage device is used commonly for the memory card and HDD. The HDD has an attachment... | 02/27/1996 |
| 5493683 | Register for identifying processor characteristics A power conversation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics ... | 02/20/1996 |
| 5490277 | Digital computation integrated circuit A digital computation integrated circuit has instruction memory for storing an instruction data, a store address designating part for designating a storing address of the instruction data in the instruction memory and for outputting the instruction data; ... | 02/06/1996 |
| 5490254 | MIL-STD-1553 interface device having autonomous operation in all modes An integrated circuit ("IC") implementing the three MIL-STD-1553 defined functions of bus controller, remote terminal, and monitor terminal implements a register-based architecture that allows for autonomous operation in all three modes, one or more modes... | 02/06/1996 |
| 5488705 | Apparatus for connecting computer devices An apparatus used in connecting computer devices which are coupled together by at least one dual line cable assembly. The invention comprises at least one converter adapter having an integrated circuit. The integrated circuit according to the invention is... | 01/30/1996 |
| 5485622 | Password processing system for computer A CPU determines whether a password canceller is connected to a system main body prior to execution of password check processing on the basis of stored password information at the start of the system. When the password canceller is connected to the system... | 01/16/1996 |
| 5483646 | Memory access control method and system for realizing the same Comparators are provided for monitoring a data write request output from CPU to a keyboard controller 113, and a request for inhibiting a memory access of 1 MB or more. Circuits are provided for generating a memory access disabling signal for disabling a ... | 01/09/1996 |
| 5481724 | Peer to peer computer-interrupt handling A coded logical interrupt signal is sent between system or subsystem units in a data processing system. The logical interrupt is sent by a sending unit, that requests the interrupt, and is sent to a receiving unit that the sending unit wishes to interrupt... | 01/02/1996 |
| 5471624 | Apparatus and method for suspending and resuming software applications on a computer A control unit of a computer system comprising a process resuming device for resuming the execution of the program it was running before the powering off operation by resuming the previous contents stored in a memory device containing registers in CPU, re... | 11/28/1995 |
| 5471588 | Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource A time multiplexing technique and corresponding circuitry which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting pro... | 11/28/1995 |
| 5471592 | Multi-processor with crossbar link of processors and memories and method of operation There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A... | 11/28/1995 |
| 5469575 | Determining a winner of a race in a data processing system A first peer entity in a data processing system comprising a plurality of similar peer entities searches for a share control file for a system privilege. The share control file contains an address of a master entity which controls the system privilege. Th... | 11/21/1995 |
| 5469576 | Front end for file access controller An improved file access controller for a data processing system, and a method for the use thereof, and more particularly, an improved front end system for a file access control system, is described. The improvement is particularly useful for security audi... | 11/21/1995 |
| 5465367 | Slow memory refresh in a computer with a limited supply of power A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a sl... | 11/07/1995 |
| 5463741 | Duplicated logic and interconnection system for arbitration among multiple information processors An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subj... | 10/31/1995 |
| 5463778 | User controlled trap handler A trap handler for a data processing system having at least two protection modes of operation includes a selective trap processor for handling certain traps without changing the protection mode of operation from the mode of operation when the trap is gene... | 10/31/1995 |
| 5459858 | Method for file transfer A method for allowing data to be transferred in parallel over several input/output channels simultaneously. When a file is opened within an application program, a system library routine tasked with allocating input/output channels checks to see if multipl... | 10/17/1995 |
| 5459872 | Software control of hardware interruptions In a computer system including an interrupt processor for interrupting a program being processed by the computer system, a sub-system for processing interrupt requests to the interrupt processor. The sub-system comprises hardware circuit for generating ha... | 10/17/1995 |
| 5457800 | Adaptable datalink interface A limited-access computer, such as an on-board flight management computer, stores a first table in a protected area of its memory defining data items in the computer memory which may be accessed, for reading and/or writing purposes, by a user such as an a... | 10/10/1995 |
| 5455913 | System and method for transferring data between independent busses A system and method for transferring a designated number d of data bytes between first and second data busses. The system includes a data buffer connected between the busses, a full counter, a partial counter, and decode logic connected to the counters. T... | 10/03/1995 |
| 5454084 | Method and apparatus for controlling bus in computer system to which expansion unit is connectable When the expansion unit is connected to the computer system to which the expansion bus controller is connectable, the bus in the computer system is controlled by the expansion bus controller of the expansion unit in place of the bus controller of the comp... | 09/26/1995 |
| 5454081 | Expansion bus type determination apparatus A circuit that automatically detects whether an input/output expansion board is connected to an EISA system or an ISA system. The circuit monitors the expansion bus for EISA slot-specific I/O cycles by sampling the bus signals AENx and BALE when either of... | 09/26/1995 |
| 5448700 | Method and system for interfacing PC to CD-ROM drives A method and a system for interfacing a PC to CD-ROM drives wherein the PC as a host can perform a different job while one of the CD-ROM drives selected as a target prepares for data to be transmitted to the host PC, thereby resulting in an increase in th... | 09/05/1995 |
| 5446847 | Programmable system bus priority network A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of... | 08/29/1995 |
| 5446846 | Distributed computer system arrangement A distributed computer system of interconnected module units which perform logical operations at different locations. A serial data bus interconnects all of the module units through a connecting device which enables the module to communicate over the seri... | 08/29/1995 |
| 5442754 | Receiving control logic system for dual bus network A system for controlling and routing messages and data received from dual system busses, through a bus interface unit, to a protocol translation logic means and to a processor in a central processing module connected onto a dual system bus network. The pr... | 08/15/1995 |
| 5440748 | Computer system capable of connecting expansion unit In a computer system, when an expansion unit is connected to a computer main body by an interface card, power supply control and I/O port selection are performed at the start of the computer system. In the power supply control, when an expansion power sup... | 08/08/1995 |
