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Vehicular Impact Signaling Device
An apparatus for the deployment of a visible plume to alert other motorists that a proximate motor vehicle has been involved in a collision.
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| Number | Title | Issue Date |
| 7870187 | Transport agnostic pull mode messaging service Transport agnostic pull mode messaging service enables clients of diverse types to send and receive messages to one another while guaranteeing delivery of messages. Client specific adapters connect to a server and pull messages waiting for them in a queue. Clients m... | 01/11/2011 |
| 6397265 | Print control apparatus for communicating with a selected external apparatus to control a printer An output apparatus for receiving input data from an information processing apparatus through a network and for forming and outputting output data, comprises: a substituting unit for substituting a process to form the output data from the input data to a ... | 05/28/2002 |
| 6182177 | Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues A method and apparatus for queuing commands. An apparatus of the present invention utilizes one or more token queues and a storage block to avoid maintaining multiple separate queues and/or to facilitate reordering of queued elements. The apparatus includ... | 01/30/2001 |
| 6149319 | Computer system host adapter for controlling signal levels to peripheral cards A method and apparatus for maintaining the voltage level of data signals supplied to an integrated circuit, such as a PCMCIA card, at the same level as power also provided to the integrated circuit. Circuitry for maintaining the voltages at the same level... | 11/21/2000 |
| 6126332 | Apparatus and method for automatically disconnecting address and data buses in a multimedia system when docking with a portable personal computer A flexible multimedia presentation system is configured to be releasably secured to a portable personal computer to provide additional features, such as a PCMCIA interface, a port replicator and other options. The system is configured to enable the unit t... | 10/03/2000 |
| 6122746 | System for powering up and powering down a server A fault tolerant computer system for powering up and powering down a server through either a local or remote client machine. The remote machine accesses the server by use of a dial-in modem connection. The power up operation brings the server to an operat... | 09/19/2000 |
| 6122700 | Apparatus and method for reducing interrupt density in computer systems by storing one or more interrupt events received at a first device in a memory and issuing an interrupt upon occurrence of a first predefined event A method and apparatus for reducing interrupt density in a computer system. One or more interrupt events received at a first device are stored in a memory and an interrupt is issued from the first device to a second device attached to the first device upo... | 09/19/2000 |
| 6088740 | Command queuing system for a hardware accelerated command interpreter engine A hardware implemented command queuing system in a hardware accelerated command interpreter engine. The command queuing system is an integral component of an autonomous hardware accelerated command interpreter type data processing engine that executes a p... | 07/11/2000 |
| 6076126 | Software locking mechanism for locking shared resources in a data processing system A shared resource lock mechanism is provided which enables processors in a mullet-processor environment which each share common resources to obtain locks on those resources using a read modify write type transaction which does not at any point in time req... | 06/13/2000 |
| 6073193 | Fail safe method and apparatus for a USB device A method and apparatus for determining and recovering from a USB micro-controller busy condition, wherein a toggle variable indicative of whether the USB micro-controller is in the busy condition or not is stored in a memory, and a counter is incremented ... | 06/06/2000 |
| 6061754 | Data bus having switch for selectively connecting and disconnecting devices to or from the bus A data bus structure is disclosed. The structure includes a data bus having a bus agent connection point and a bus switch to selectively connect or disconnect the connection point to or from the data bus. A method of reconfiguring a data bus structure is ... | 05/09/2000 |
| 6058449 | Fault tolerant serial arbitration system A serial arbitration system utilizes an arbitration token containing a start bit, a request bit, a set of priority bits, and an error detection bit. The arbitration token is sent to each of the other processors (20, 21, 22) and is used to arbitrate contro... | 05/02/2000 |
| 6038627 | SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transis... | 03/14/2000 |
| 6035349 | Structure of portable multimedia data input/output processor and method for driving the same Potable multimedia terminal which is small and consumes low power, can process a large quantity of multimedia data such as video and audio data. Portable multimedia data input/output processor can be made smaller by using a pen as an input device and can ... | 03/07/2000 |
| 6029236 | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM A field programmable gate array (FPGA) comprising a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM is disclosed. In accordance with the present ... | 02/22/2000 |
| 6029217 | Queued arbitration mechanism for data processing system A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the syst... | 02/22/2000 |
| 6026494 | Algorithm to reduce power consumption of an auto-negotiating ethernet transceiver A method and apparatus for reducing power consumption of an auto-negotiating ethernet transceiver by enabling a driver for the transceiver to alternate between a typical higher-power energy consumption mode to a lower-power energy consumption mode when a ... | 02/15/2000 |
| 6026218 | Computer system employing a bus snooping multimedia subsystem for implementing video multicast transactions A bus snooping multimedia subsystem for implementing video multicast transactions. A multimedia data source such as a video input digitizer is coupled to an expansion bus of a computer system. A plurality of multimedia destination subsystems are further c... | 02/15/2000 |
| 6021460 | Protect circuit of register A protect circuit of a register which can positively protect the contents of a register in a runaway of a program in a microcomputer or the like. It includes a first register for holding data on a data bus of a microcomputer at a first time instant, a sec... | 02/01/2000 |
| 6016526 | Method and apparatus for transferring data between buses having differing ordering policies via the use of autonomous units A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data to the second bus... | 01/18/2000 |
| 6016518 | Automatic master/slave designation for computer peripherals The present invention provides an apparatus that automatically designates a peripheral device as either a master or slave in response to the peripheral device connections when power is turned on. The apparatus comprises first and second connectors coupled... | 01/18/2000 |
| 6014750 | Techniques for distributing/supplying intra-computer DC power to external peripheral devices of a computer system Apparatus for adapting a personal computer unit having an internal power supply and a sidewall adapted for supplying associated external peripherals with DC power from the power supply. For each peripheral, the sidewall is provided with a removable power ... | 01/11/2000 |
| 6012124 | Disk system with activation control of disk drive motors With respect to the disk drives provided power from a single power source in a disk drive system, start up power is first supplied to a first start-up group of the disks, preferably comprising all of the master disks, with the size of the group being sele... | 01/04/2000 |
| 6009486 | Cardbus docking station A computer system with a PC Card external connector sends signals to PCI devices as if respective PC Card functions. A cooperating docking station connects to the PC Card connector and so processes the PC Card signals that a set of signals for supporting ... | 12/28/1999 |
| 6006281 | Network printing system with data merge feature A printing subsystem for use in a network printing system, having a database communicating with a client browser, is provided. The database includes a plurality of data sets and the client browser includes a program with a set of instructions for displayi... | 12/21/1999 |
| 6003139 | Computer system including power supply circuit with controlled output power A computer system includes a computer system unit and a power supply circuit. The power supply circuit is coupled to receive input power and generate output power. This circuit includes a circuit to generate a control signal that is related to the power l... | 12/14/1999 |
| 5999998 | ISA adaptor card Use of ISA Adapter Card (ISAAC) to insure timing of application of power and logic to ISA, SCSA and MVIP Cards when those cards are plugged into standard ISA connectors of the ISAAC and the ISAAC is subsequently plugged into an active ISA, SCSA, and/or MV... | 12/07/1999 |
| 5999742 | Dual latch data transfer pacing logic using a timer to maintain a data transfer interval A dual latch character pacing circuit on a semiconductor chip controls data transfer between a pair of microprocessor which have significantly different data transfer rates. A first and second latch are connected in a parallel data path between the two mi... | 12/07/1999 |
| 5996034 | Bus bridge verification system including device independent bus monitors A transaction checking system and method to verify bus bridge designs in multi-master bus systems. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine obj... | 11/30/1999 |
| 5991842 | Communication system for providing digital data transfer, electronic equipment for transferring data using the communication system, and an interface control device An electronic equipment for communications with other nodes via a serial bus interface. The electronic equipment has a plurality of functions, and stores a plurality piece of information representative of the plurality of functions. The communication syst... | 11/23/1999 |
| 5991839 | Computer system having computer main body and expansion unit A computer main body has a system bus. The system bus is connected to a PCI-DS bridge. A docking station has a plurality of expansion devices for expanding the functions of the computer main body. The computer main body is attached to the docking station ... | 11/23/1999 |
| 5987550 | Lock mechanism for shared resources in a data processing system A shared resource lock mechanism is provided which enables processors in a multi-processor system which each share common resources to obtain locks on those resources using a transactions which minimizes the amount of time system resources are unavailable... | 11/16/1999 |
| 5987554 | Method of controlling the transfer of information across an interface between two buses A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second... | 11/16/1999 |
| 5987614 | Distributed power management system and method for computer Structure and method are provided for reducing power consumption in a computer system without sacrificing computer performance or inhibiting a computer user's rapid access to the computer. An identifier, such as a device address, network address, serial n... | 11/16/1999 |
| 5983301 | Method and system for assigning a direct memory access priority in a packetized data communications interface device In a PCI-interface device (20), assigning highest DMA channel (74) priority is based on the DMA channel number associated with the data transfer currently active on the physical media interface. The present invention supplies this priority information rel... | 11/09/1999 |
| 5983296 | Method and apparatus for terminating busses having different widths A method and apparatus for providing automatic termination of cables coupled to an adapter card is described. The presence or absence of devices attached to such cables are sensed. A terminator circuit is selectively activated to provide termination for t... | 11/09/1999 |
| 5983299 | Priority request and bypass bus To reduce latency for priority requests in a bus system, non-priority requests to a bus device are separated from priority requests so that the priority requests can be processed before the non-priority requests. Priority requests are transferred over a p... | 11/09/1999 |
| 5978921 | Computer system and control method thereof A portable computer system made up of a voltage level detecting portion for detecting the output voltage level of a battery; a switching portion connected between the battery and at least one peripheral device for turning on/off the peripheral device; a b... | 11/02/1999 |
| 5974553 | Method for powering elements connected in a two-wire bus network transmitting both power supply and data information pulses The present invention relates to a powering method for elements connected in a two-wire bus type network wherein information frames of predetermined length are transmitted at predetermined times. The method consists of regularly sending on the two-wire bu... | 10/26/1999 |
| 5974490 | Plural disk unit apparatus providing high-density mounting of disk units and peripheral units A mother board provided in a plural disk unit, which is formed with an interconnection pattern containing high speed control buses such as SCSI buses, is disposed at the central portion of a housing. A plurality of disk units capable of being removably in... | 10/26/1999 |
