Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 8188535 | Nonvolatile semiconductor memory device and manufacturing method thereof An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and ... | 05/29/2012 |
| 8189369 | Semiconductor device There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word li... | 05/29/2012 |
| 8189419 | Apparatus for nonvolatile multi-programmable electronic fuse system Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second ... | 05/29/2012 |
| 8188454 | Forming a phase change memory with an ovonic threshold switch A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to... | 05/29/2012 |
| 8189363 | Resistance change memory A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each incl... | 05/29/2012 |
| 8189368 | Cell structure for dual port SRAM A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port includin... | 05/29/2012 |
| 8184500 | Semiconductor memory device and method for operating the same A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an ac... | 05/22/2012 |
| 8183652 | Non-volatile magnetic memory with low switching current and high thermal stability A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the... | 05/22/2012 |
| 8179734 | Semiconductor device A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write vo... | 05/15/2012 |
| 8179711 | Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory c... | 05/15/2012 |
| 8174891 | Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices A non-volatile semiconductor memory device includes a NAND cell unit including a plurality of electrically rewritable non-volatile memory cells serially connected. The NAND cell unit has one end connected to a bit line via a first selection gate transistor and the o... | 05/08/2012 |
| 8174920 | Semiconductor memory device and driving method of the same A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch ... | 05/08/2012 |
| 8174890 | Non-volatile semiconductor storage device A memory cell array has plural memory strings arranged therein, each of which including a plurality of electrically-rewritable memory transistors and selection transistors. Each memory string includes a body semiconductor layer including four or more columnar portio... | 05/08/2012 |
| 8174903 | Method of operating nonvolatile memory device A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes prechargi... | 05/08/2012 |
| 8174898 | Sense amplifier and data sensing method thereof A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing th... | 05/08/2012 |
| 8174906 | Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively,... | 05/08/2012 |
| 8174904 | Memory array and method of operating one of a plurality of memory cells An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of t... | 05/08/2012 |
| 8169845 | Apparatus and methods for sense amplifiers Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to... | 05/01/2012 |
| 8164968 | Voltage down converter for high speed memory A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to... | 04/24/2012 |
| 8159859 | Semiconductor storage device A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to... | 04/17/2012 |
| 8154904 | Programming reversible resistance switching elements A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techni... | 04/10/2012 |
| 8154085 | Nonvolatile semiconductor memory has resistors including electrode layer formed on low resistance layer adjacent to mask film A nonvolatile semiconductor memory includes memory cell transistors and resistors. Each memory cell transistor has source/drain diffusion layers provided in a semiconductor substrate, a first gate insulating film located between the source/drain diffusion layers, a ... | 04/10/2012 |
| 8154908 | Nonvolatile semiconductor storage device and data writing method therefor A nonvolatile semiconductor storage device includes: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for m... | 04/10/2012 |
| 8154069 | NAND flash memory with selection transistor having two-layer inter-layer insulation film A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate... | 04/10/2012 |
| 8153447 | Nonvolatile ferroelectric perpendicular electrode cell, FeRAM having the cell and method for manufacturing the cell A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second... | 04/10/2012 |
| 8154070 | Semiconductor memory device and method of manufacturing the same A nonvolatile memory includes a semiconductor substrate having a body member and a step member formed on the body member, a highly doped first well layer formed on the step member, a control electrode formed on the step member, a first and a second diffusion layers ... | 04/10/2012 |
| 8154004 | Hybrid MRAM array structure and operation This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher ... | 04/10/2012 |
| 8154911 | Memory device and method of writing data to a memory device A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of th... | 04/10/2012 |
| 8154934 | Semiconductor memory device and memory system having the same A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output un... | 04/10/2012 |
| 8148708 | Resistive memory device and method of fabricating the same A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical se... | 04/03/2012 |
| 8149609 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells each provided at individual intersection between a first wiring and a second wiring, the memory cell comprising a variable resistive element, and predetermined numbers o... | 04/03/2012 |
| 8149641 | Active cycle control circuit for semiconductor memory apparatus An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during t... | 04/03/2012 |
| 8148780 | Devices and systems relating to a memory cell having a floating body Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first ... | 04/03/2012 |
| 8149628 | Operating method of non-volatile memory device A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the... | 04/03/2012 |
| 8144527 | Semiconductor memory device A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an outpu... | 03/27/2012 |
| 8144532 | Semiconductor memory device and method of controlling same A memory cell is provided at an intersection of a word line and a bit line. A sense amplifier circuit senses and amplifies a signal on the bit line. Replica circuits include a replica cell configured to retain certain data fixedly. A signal detection circuit detects... | 03/27/2012 |
| 8144502 | Static random access memory Included are a memory cell, a first metal interconnection, a variable capacitance circuit and a connection switch. The memory cell includes cross-coupled first and second inverters which are connected to a power supply node. The first metal interconnection is connec... | 03/27/2012 |
| 8143611 | Phase-change memory element, phase-change memory cell, vacuum processing apparatus, and phase-change memory element manufacturing method A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when suppli... | 03/27/2012 |
| 8142159 | Fan and motor thereof A fan includes a plurality of blades and a motor. The motor includes a hub and a shaft having an end connected to the hub, a bushing, a bearing, and an oil-sealing structure. The blades are connected with and surrounding around the hub. The bushing is for supporting... | 03/27/2012 |
| 8143663 | Non-volatile memory device having selection gates formed on the sidewalls of dielectric layers A non-volatile memory device having a split gate type cell structure, a method for fabricating the same, and a method for fabricating a semiconductor device by using the same are provided. A non-volatile memory device includes a substrate, a plurality of patterned t... | 03/27/2012 |
