Did You Know...
...that two musicians were responsible for the invention of color print film? Fascinated by photography, Leopold Godowsky and Leopold Mannes worked together to produce an easy-to-use, practical color film. They worked full time as music teachers and gave concerts while experimenting during their off hours in Mannes' kitchen. Their success earned them full-time, well-paying jobs at Kodak and their efforts resulted in Kodachrome film, which was introduced in 1935.
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| Number | Title | Issue Date |
| 7408809 | Method and apparatus for programming single-poly pFET-based nonvolatile memory cells Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event... | 08/05/2008 |
| 7405995 | Semiconductor storage device A semiconductor storage device has a simple control circuit that is added to a general one-port RAM. Taking a port-A clock signal as the reference, the control circuit generates a select signal that selects a port A during the period from elapse of a first predeterm... | 07/29/2008 |
| 6731539 | Memory with offset bank select cells at opposite ends of buried diffusion lines A compact contactless Flash memory architecture has memory cells instead of isolation regions between adjacent diffused lines in rows of a bank and thereby increases the density of memory cells in the bank when compared to prior architectures. Diffused lines in the ... | 05/04/2004 |
| 6693845 | Semiconductor device having PLL-circuit A semiconductor device includes a clock input terminal to which external clocks are supplied; a PLL circuit, which is supplied with the external clocks and generate first internal clocks; a logic circuit, which operates in synchronization with the interna... | 02/17/2004 |
| 6693815 | Semiconductor associative memory An associative memory composed of plural chips or a single chip which is preferably used in the fields of bandwidth compression for video images in mobile communication terminals and artificial intelligence systems. The associative memory is a small-area ... | 02/17/2004 |
| 6690614 | Semiconductor integrated circuit device A semiconductor chip is divided into a first semiconductor region surrounded by pads and a region outside the pads. A memory is arranged at the region outside the pads. A memory arranged in the first semiconductor region and the memory arranged outside th... | 02/10/2004 |
| 6687170 | System and method for storing parity information in fuses A system and method for determining the accuracy of the states of fuses by changing, or not changing, the state of additional fuses. The system includes a memory including addressable storage elements, address fuses whereby each fuse includes a link in a ... | 02/03/2004 |
| 6639818 | Differential non-volatile content addressable memory cell and array A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate tr... | 10/28/2003 |
| 6608788 | Bitline precharge An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing dens... | 08/19/2003 |
| 6606277 | Semiconductor memory device To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the da... | 08/12/2003 |
| 6603676 | Method of managing optical disk drive parameters A method of writing in or reading out data on a medium is provided. The method comprises receiving mechanism driving information corresponding to a type of a drive unit from an external apparatus, the drive unit being configured to write in or read out da... | 08/05/2003 |
| 6597596 | Content addressable memory having cascaded sub-entry architecture A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gat... | 07/22/2003 |
| 6597618 | Magnetic tunnel junction magnetic random access memory A circuit for controlling a read operation for a magnetic random access memory (MRAM) comprising an array of magnetic tunnel junctions (MTJ) having conducting row and column lines attached thereto. The circuitry comprises a current supply for providing a ... | 07/22/2003 |
| 6594178 | Method for optimizing distribution profile of cell threshold voltages in NAND-type flash memory device A method is operable in a non-volatile memory device of a type having a plurality of blocks formed of a plurality of memory strings in which a plurality of memory cells are connected in series in which a programming operation is conducted after erasing me... | 07/15/2003 |
| 6594185 | Write-inhibit circuit, semiconductor integrated circuit using the same, ink cartridge including the semiconductor integrated circuit, and ink-jet recording apparatus Chip area and operating current is reduced in a chip having a write-inhibit circuit that uses a data-writing request signal WR and a write-control signal WRITE to inhibit data writing. By comparing a reference current Iref and a drive current ID, a curren... | 07/15/2003 |
| 6594193 | Charge pump for negative differential resistance transistor An integrated circuit device includes a charge pump for providing a bias signal to a field effect transistor (FET) that is capable of operating in a negative differential resistance mode. The bias signal is applied to a gate of the NDR FET to control the ... | 07/15/2003 |
| 6590807 | Method for reading a structural phase-change memory A cell in a structural phase-change memory is programmed by raising cell voltage and cell current to programming threshold levels, and then lowering these to quiescent levels below their programming levels. A precharge pulse is then applied which raises t... | 07/08/2003 |
| 6590813 | Semiconductor memory and method of controlling the same A semiconductor memory has a memory cell array, a boosted voltage generator to generate a boosted voltage and a decoder to select memory cells in said memory cell array in response to an address signal. The voltage generator is activated in response to in... | 07/08/2003 |
| 6590810 | Source biasing circuit for flash EEPROM A source biasing circuit for providing a negative biasing voltage to an electrically-erasable, programmable read-only memory (EEPROM) circuit during a read or programming operation. The negative biasing voltage helps overcome the source line resistance th... | 07/08/2003 |
| 6587376 | Flash memory cell for high efficiency programming A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by apply... | 07/01/2003 |
| 6587364 | System and method for increasing performance in a compilable read-only memory (ROM) A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. Each ... | 07/01/2003 |
| 6587386 | Semiconductor memory having multiple redundant columns with offset segmentation boundaries A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into fou... | 07/01/2003 |
| 6584020 | Semiconductor memory device having intermediate voltage generating circuit In a bit line reference potential (VBL) generating circuit, a pad is connected via a transfer gate to a reference node in a reference stage. During a device evaluation test, the transfer gate is turned on in response to a test signal so that a voltage is ... | 06/24/2003 |
| 6584010 | Selective device coupling Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conducta... | 06/24/2003 |
| 6584035 | Supply noise reduction in memory device column selection Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtere... | 06/24/2003 |
| 6584025 | Read compression in a memory A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in paralle... | 06/24/2003 |
| 6580651 | Reduced power bit line selection in memory circuits A method for reducing power consumption during bit line selection in memory circuits is disclosed. According to an exemplary aspect of the method, two adjacent memory cell arrays in memory circuits generally share a row of bit-line sense amplifiers. These... | 06/17/2003 |
| 6580637 | Semiconductor memory architecture A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the se... | 06/17/2003 |
| 6577525 | Sensing method and apparatus for resistance memory device An MRAM memory integrated circuit is disclosed. Resistance, and hence logic state, is determined by discharging a first charged capacitor through an unknown cell resistive element to be sensed at a fixed voltage, and a pair of reference capacitors. The ra... | 06/10/2003 |
| 6577537 | Flash memory cell for high efficiency programming A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by apply... | 06/10/2003 |
| 6577531 | Nonvolatile memory and semiconductor device A nonvolatile memory capable of acting at each 1 bit and having a high integration density. A small-sized semiconductor device of multiple high functions having such nonvolatile memory. The nonvolatile memory is constructed to have a memory cell composed of tw... | 06/10/2003 |
| 6577553 | Semiconductor memory device Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a pr... | 06/10/2003 |
| 6577535 | Method and system for distributed power generation in multi-chip memory systems Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are disclosed. The various voltage levels can be produced by charge pump and regulator circuitry within the memory syst... | 06/10/2003 |
| 6577546 | Semiconductor integrated circuit and operating method A semiconductor integrated circuit (50) having normal operation mode and a burn-in mode is provided. The semiconductor integrated circuit (50) can include a memory (14) and a logic circuit (9). The memory (14) may operate in response to input signals (inp... | 06/10/2003 |
| 6574138 | Memory cell configuration and method for operating the configuration A memory cell configuration has memory cells that each contain two magnetoresistive elements. If the two magnetoresistive elements of each memory cell are magnetized in such a way that they have different resistances, the information stored in the memory ... | 06/03/2003 |
| 6574142 | Integrated circuit with flash memory This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by pro... | 06/03/2003 |
| 6570803 | Memory system capable of increasing utilization efficiency of semiconductor memory device and method of refreshing the semiconductor memory device A memory system, which is capable of increasing the utilization efficiency of a semiconductor memory device, and a method of refreshing the semiconductor memory device are provided. The memory controller can selectively perform a refresh operation on a pa... | 05/27/2003 |
| 6570795 | Defective memory component of a memory device used to represent a data bit in a bit sequence A memory device includes memory components that represent a logic value corresponding to a data bit in a bit sequence. A defective memory component in the memory device represents a data bit in the bit sequence. An additional memory component in the memor... | 05/27/2003 |
| 6570807 | Intermediate boosted array voltage Two voltage pumps, or a single voltage pump having two pump circuits, are given wherein one pump, or pump circuit, produces a normal pumped voltage and the other pump, or pump circuit, produces an intermediate pumped voltage which is less than the normal ... | 05/27/2003 |
| 6570810 | Contactless flash memory with buried diffusion bit/virtual ground lines A contactless Flash memory has memory cells between each pair of adjacent diffused lines and about half as many metal lines as diffused lines. Bank select cells at the top of a bank in the memory connect the metal lines to pairs of diffused lines that are... | 05/27/2003 |
