| Patent No. | Patent Title: |
| 5701092 | OR array architecture for a programmable logic device |
| 5635859 | Level converting circuit |
| 5606270 | Dynamic clocked inverter latch with reduced charge leakage |
| 5600261 | Output enable access for an output buffer |
| 5598110 | Detector circuit for use with tri-state logic devices |
| 5598105 | Elementary cell for constructing asynchronous superconducting log... |
| 5594369 | Open-drain fet output circuit |
| 5594368 | Low power combinational logic circuit |
| 5592108 | Interface circuit adapted for connection to following circuit usi... |
| 5592102 | Means and apparatus to minimize the effects of silicon processing... |
| 5587668 | Semiconductor devices utilizing neuron MOS transistors |
| 5587669 | Programmable application specific integrated circuit and logic ce... |
| 5583456 | Differentially coupled AND/NAND and XOR/XNOR circuitry |
| 5583454 | Programmable input/output driver circuit capable of operating at ... |
| 5578943 | Signal transmitter and apparatus incorporating same |
| 5578944 | Signal receiver and apparatus incorporating same |
| 5576640 | CMOS driver for fast single-ended bus |
| 5576643 | Data transfer circuit device |
| 5572149 | Clock regeneration circuit |
| 5572152 | Logic circuit with the function of controlling discharge current ... |
| 5572150 | Low power pre-discharged ratio logic |
| 5570046 | Lead frame with noisy and quiet VSS and VDD... |
| 5570043 | Overvoltage tolerant intergrated circuit output buffer |
| 5570036 | CMOS buffer circuit having power-down feature |
| 5570037 | Switchable differential terminator |
| 5568070 | Multiplexer w/ selective switching for external signals |
| 5568062 | Low noise tri-state output buffer |
| 5568061 | Redundant line decoder master enable |
| 5568066 | Sense amplifier and or gate for a high density programmable logic... |
| 5565795 | Level converting circuit for reducing an on-quiescence current |
| 5565798 | Self-timed control circuit for self-resetting logic circuitry |
| 5561694 | Self-timed driver circuit |
| 5559459 | Clock signal generation arrangement including digital noise reduc... |
| 5557488 | Gimbaled micro-head/flexure/conductor assembly and system |
| 5557219 | Interface level programmability |
| 5550691 | Size-independent, rigid-disk, magnetic, digital-information stora... |
| 5550491 | Current-mode logic circuit |
| 5543732 | Programmable logic array devices with interconnect lines of vario... |
| 5541527 | PECL buffer |
| 5541528 | CMOS buffer circuit having increased speed |
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