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| Number | Title | Issue Date |
| 8104030 | Mechanism to restrict parallelization of loops A computer implemented method, computer usable program code, and a system for parallelizing a loop. A parameter that will be used to limit parallelization of the loop is identified to limit parallelization of the loop. The parameter specifies a minimum number of loo... | 01/24/2012 |
| 8087012 | Eliminating maximum/minimum operations in loop bounds A technique is provided for eliminating maximum and minimum expressions within loop bounds are provided. A loop in a code is identified. The loop is determined to meet conditions, which require an upper loop bound and a lower loop bound to contain maximum and minimu... | 12/27/2011 |
| 8060870 | System and method for advanced polyhedral loop transformations of source code in a compiler A system and method for advanced polyhedral loop transformations of source code in a compiler are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for... | 11/15/2011 |
| 8056069 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 11/08/2011 |
| 8028281 | Run-Time parallelization of loops in computer programs using bit vectors Parallelization of loops is performed for loops having indirect loop index variables and embedded conditional statements in the loop body. Loops having any finite number of array variables in the loop body, and any finite number of indirect loop index variables can ... | 09/27/2011 |
| 8010957 | Compiler for eliminating redundant read-modify-write code sequences in non-vectorizable code A computer implemented method, apparatus, and computer usable program code for eliminating redundant read-modify-write code sequences in non-vectorizable code. Code is received comprising a sequence of operations. The sequence of operations includes a loop. Non-vect... | 08/30/2011 |
| 7962906 | Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data A compiler includes a mechanism for employing multiple synergistic processors to execute long vectors. The compiler receives a single source program. The compiler identifies vectorizable loop code in the single source program and extracts the vectorizable loop code ... | 06/14/2011 |
| 7937695 | Reducing number of exception checks Based on operations within an uncounted loop of source code, one or more calculations are generated for determining, at runtime, an expected number of iterations through which the uncounted loop can iterate before encountering an exception corresponding to at least ... | 05/03/2011 |
| 7908256 | Speculative computation lock coarsening through the use of localized lock reservation A computer-implementable method, system and computer-usable medium. One or more objects among a plurality of objects can be processed utilizing a data-processing apparatus/system. One or more lock reservations can be applied among a group of lock reservations over a... | 03/15/2011 |
| 7890943 | Code optimization based on loop structures Instructions that have no dependence constraint between them and other instructions in a loop of a critical section may be moved out of the critical section so that the size of the critical section may be reduced. A flow graph of a program including the critical sec... | 02/15/2011 |
| 7890942 | Array value substitution and propagation with loop transformations through static analysis A method and system for substituting array values (i.e., expressions) in a program at compile time. An initialization of an array is identified in a loop. The initialization is an assignment of an expression (i.e., a constant or a function of an induction variable t... | 02/15/2011 |
| 7873954 | Stack unique signatures for program procedures and methods Stack signature marking segments are inserted into re-entrant programming source code modules prior to compilation of the modules at each code module entry point and at each code module exit point, followed by producing one or more executable programs from the progr... | 01/18/2011 |
| 7865886 | Blocking of nested loops having feedback or feedforward indexes A method and apparatus for to blocking nested loops having feedback or feedforward indexing. An embodiment of a method includes receiving a computer code segment, the segment including a first inner loop and a second outer loop, the inner loop being within the outer... | 01/04/2011 |
| 7856629 | Compiler apparatus A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of ... | 12/21/2010 |
| 7849453 | Method and apparatus for software scouting regions of a program One embodiment of the present invention provides a system that generates code for software scouting the regions of a program. During operation, the system receives source code for a program. The system then compiles the source code. In the first step of the compilat... | 12/07/2010 |
| 7823141 | Using a concurrent partial inspector loop with speculative parallelism A method for executing a loop in an application that includes executing iterations in a first segment of the loop by a base thread, logging memory transactions that occur during execution of iterations in the first segment by a co-inspector thread to obtain a co-ins... | 10/26/2010 |
| 7814468 | Method for loop reformulation A method for loop reformulation is provided such that a single exit ill-formed loop (SEIFL) can be reformulated into a reformulated code block that contains a transformed well-formed loop (TWFL). A SEIFL loop is a loop that can exit from the loop body of the loop. A... | 10/12/2010 |
| 7810032 | System and method for performing over time statistics in an electronic spreadsheet environment A method and system for computing statistical parameters for sets of data items, by executing instructions of a computer program that is coded within a spreadsheet. Each set is generated in a time sequence that is specific to each set. For each time sequence, each d... | 10/05/2010 |
| 7793278 | Systems and methods for affine-partitioning programs onto multiple processing units Systems and methods perform affine partitioning on a code stream to produce code segments that may be parallelized. The code segments include copies of the original code stream with conditional inserted that aid in parallelizing code. The conditional is formed by de... | 09/07/2010 |
| 7788659 | Method of converting computer program with loops to one without loops The present invention is a method of eliminating loops from a computer program by receiving the program, graphing its function and control, identifying its entry point, and identifying groups of loops connected to its entry point. Stop if there are no such groups. O... | 08/31/2010 |
| 7689980 | Splitting the computation space to optimize parallel code Linear transformations of statements in code are performed to generate linear expressions associated with the statements. Parallel code is generated using the linear expressions. Generating the parallel code includes splitting the computation-space of the statements... | 03/30/2010 |
| 7665079 | Program execution method using an optimizing just-in-time compiler It is one object of the present invention to provide a program execution method for performing greater optimization. A program execution apparatus according to the present invention performs a transfer from an interpreter process to a compiled code process in the co... | 02/16/2010 |
| 7581215 | Dependency analysis system and method We present a technique to perform dependence analysis on more complex array subscripts than the linear form of the enclosing loop indices. For such complex array subscripts, we decouple the original iteration space and the dependence test iteration space and link th... | 08/25/2009 |
| 7530063 | Method and system for code modification based on cache structure A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a mod... | 05/05/2009 |
| 7506331 | Method and apparatus for determining the profitability of expanding unpipelined instructions A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded. ... | 03/17/2009 |
| 7428731 | Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators A method, machine readable medium, and system are disclosed. In one embodiment the method comprises collecting a loop trip count continuously during runtime of a region of code being executed that contains a loop, categorizing the trip count to identify one or more ... | 09/23/2008 |
| 7421687 | Optimizing branch condition expressions in a JIT compiler A Java virtual machine includes a just in time (JIT) Java compiler. The JIT compiler includes at least one optimizer. Each of the at least one optimizer includes logic for recognizing a pattern in a received Java byte code, logic for optimizing the recognized patter... | 09/02/2008 |
| 7415700 | Runtime quality verification of execution units One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of ... | 08/19/2008 |
| 7404183 | Transforming locks in software loops An improved method and system for acquisition and release of locks within a software program is disclosed. In an exemplary embodiment, a lock within a loop is transformed by relocating acquisition and release instructions from within the loop to positions outside th... | 07/22/2008 |
| 7395531 | Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler... | 07/01/2008 |
| 7395419 | Macroscalar processor architecture A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive o... | 07/01/2008 |
| 7386842 | Efficient data reorganization to satisfy data alignment constraints An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The ... | 06/10/2008 |
| 7373642 | Defining instruction extensions in a standard programming language A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method inclu... | 05/13/2008 |
| 7367024 | Compiler-driven dynamic memory allocation methodology for scratch-pad based embedded systems A highly predictable, low overhead and yet dynamic, memory allocation methodology for embedded systems with scratch-pad memory is presented. The dynamic memory allocation methodology for global and stack data (i) accounts for changing program requirements at runtime... | 04/29/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7363338 | Selective assembly loading and execution based on platform capabilities An arrangement is provided for selectively loading and executing an assembly based on platform capabilities. When an application that includes at least one platform capability-dependent assembly realized to perform a function is initiated on a platform of a device, ... | 04/22/2008 |
| 7360205 | Minimizing interaction costs among components of computer programs A system and method for minimizing total cost of interaction among components of a computer program which are each characterized by at least one implementation property. A implementation property may, for example, be a choice of string representation (e.g. ASCII, UN... | 04/15/2008 |
| 7360207 | Method and system to analyze inlined functions A method and a system for examining an inlined function using a performance analysis tool are described. An inlined function is identified in computer code. Upon identification of the inlined function, and for example in response to executing a breakpoint associated... | 04/15/2008 |
| 7353505 | Tracing the execution path of a computer program The invention relates to tracing the execution path of a computer program comprising at least one module including a plurality of instructions. At least one of these instructions is a branch instruction. Each branch instruction is identified and evaluated to be one ... | 04/01/2008 |
| 7353491 | Optimization of memory accesses in a circuit design Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset... | 04/01/2008 |
