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| Number | Title | Issue Date |
| 8087010 | Selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework Mechanisms for selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based a... | 12/27/2011 |
| 8024717 | Method and apparatus for efficiently processing array operation in computer system An apparatus and a method for processing an array in a loop in a computer system, including: applying loop unrolling to a multi-dimensional array included in a loop based on a predetermined unrolling factor to generate a plurality of unrolled multi-dimensional array... | 09/20/2011 |
| 8006238 | Workload partitioning in a parallel system with hetergeneous alignment constraints A process, compiler, computer program product and system for workload partitioning in a heterogeneous system. The process includes determining heterogeneous alignment constraints in the workload, partitioning a portion of tasks to a processing element sensitive to a... | 08/23/2011 |
| 7877742 | Method, system, and computer program product to generate test instruction streams while guaranteeing loop termination A method, system, and computer program product for generating terminating, pseudo-random test instruction streams, including forward and backward branching instructions. A first instruction stream is generated, including at least one backward branching instruction a... | 01/25/2011 |
| 7774766 | Method and system for performing reassociation in software loops Various embodiments of the present invention relate to methods and systems for optimizing an intermediate code in a compilation logic. The intermediate code is optimized by performing reassociation in software loops. The intermediate code includes at least one criti... | 08/10/2010 |
| 7712091 | Method for predicate promotion in a software loop A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a dependency link between two instructions and contains a dependee and ... | 05/04/2010 |
| 7685582 | Looping constructs in object model software A system and method for providing looping constructs to an object model where the looping construct is contained within a child object of a parent object. The system and method further provides for an enumerator to map between indexes representing a collection of ob... | 03/23/2010 |
| 7549146 | Apparatus, systems, and methods for execution-driven loop splitting and load-safe code hosting Techniques for execution-driven loop splitting and load-safe code hosting are provided. Compiled code includes statements associated with an original loop and statements associated with an alternative loop. The alternative loop reproduces the original loop except fo... | 06/16/2009 |
| 7487497 | Method and system for auto parallelization of zero-trip loops through induction variable substitution A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is kno... | 02/03/2009 |
| 7478377 | SIMD code generation in the presence of optimized misaligned data reorganization Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel techique to efficient... | 01/13/2009 |
| 7475392 | SIMD code generation for loops with mixed data lengths Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel technique to efficien... | 01/06/2009 |
| 7395531 | Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler... | 07/01/2008 |
| 7386842 | Efficient data reorganization to satisfy data alignment constraints An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The ... | 06/10/2008 |
| 7373642 | Defining instruction extensions in a standard programming language A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method inclu... | 05/13/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7353491 | Optimization of memory accesses in a circuit design Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset... | 04/01/2008 |
| 7343595 | Method, apparatus and computer program for executing a program by incorporating threads There is provided a method for executing a program comprising a function call and one or more subsequent instructions. The method comprises processing, on a first thread, a function defined by the function call, the function having one or more programmer predefined ... | 03/11/2008 |
| 7340732 | Updating profile frequency for procedure inlining A method and apparatus for frequency-updating for procedure inlining. The frequency-updating scheme assumes the call graph of a program has no cycles. It keeps the frequency for each procedure as accurate as that before inlining. Using the present invention, the run... | 03/04/2008 |
| 7340733 | Optimizing source code for iterative execution An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer p... | 03/04/2008 |
| 7337439 | Method for increasing the speed of speculative execution A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been sele... | 02/26/2008 |
| 7331043 | Detecting and mitigating soft errors using duplicative instructions Software techniques are employed to mitigate soft errors. In particular, a compiler (or other executable code generator) may emit otherwise duplicative instructions targeting otherwise duplicative storage locations to facilitate run-time detection and, in some cases... | 02/12/2008 |
| 7316012 | System, method, and apparatus for spilling and filling rotating registers in software-pipelined loops An efficient method for software-pipelining (SWP) of loops to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer. In one example embodiment, this is accomplished by spilling and filling multipl... | 01/01/2008 |
| 7313787 | Compiler and method for optimizing object codes for hierarchical memories Different optimizing methods are applied in response to such a memory hierarchy to which a program mainly accesses when the program is executed. A memory hierarchy to which a program mainly accesses is designated by a user with employment of either a compiler option... | 12/25/2007 |
| 7313788 | Vectorization in a SIMdD DSP architecture A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture... | 12/25/2007 |
| 7305676 | Communication device configured for real time processing of user data to be transmitted A communication device is provided which has a programmable multichannel signal processor for real time processing of user data, which are to be transmitted, within the framework of a plurality of real time applications. The real time applications are each assigned ... | 12/04/2007 |
| 7302680 | Data repacking for memory accesses A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is... | 11/27/2007 |
| 7295672 | Method and apparatus for fast RC4-like encryption A method and apparatus for encrypting information. In one embodiment, a method for encrypting information includes obtaining a value A from an array having a plurality of values and determining a value B based on the value A in a first pipeline stage. In a second pi... | 11/13/2007 |
| 7293258 | Data processor and method for using a data processor with debug circuit A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action ... | 11/06/2007 |
| 7281242 | Flexible and extensible Java bytecode instrumentation system Code can be injected into a compiled application through the use of probes comprised of instrumentation code. Probes can be implemented in a custom high level language that hides low level instruction details. A directive file contains instructions on injecting a pr... | 10/09/2007 |
| 7266809 | Software debugger and software development support system for microcomputer operable to execute conditional execution instruction A software debugger tangibly embodied on a computer readable medium may display a microcomputer program being debugged so that a halt address at which the execution of the program is caused to halt can be distinguished from other addresses. When performing step-by-s... | 09/04/2007 |
| 7263692 | System and method for software-pipelining of loops with sparse matrix routines A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming s... | 08/28/2007 |
| 7257810 | Method and apparatus for inserting prefetch instructions in an optimizing compiler One embodiment of the present invention provides a system that generates code to perform anticipatory prefetching for data references. During operation, the system receives code to be executed on a computer system. Next, the system analyzes the code to identify data... | 08/14/2007 |
| 7251810 | Minimal instrumentation for lossless call profiling A method, apparatus, and software are disclosed for collecting information relating to the execution of an application for use in analyzing the performance of the application. Probes are inserted at only those points in the application that would yield non-redundant... | 07/31/2007 |
| 7243342 | Methods and apparatus for determining if a user-defined software function is a memory allocation function during compile-time Methods and apparatus are disclosed for determining if a user-defined software function is a memory allocation function during compile-time. The methods and apparatus determine if a user-defined function returns a new memory object every time the user-defined functi... | 07/10/2007 |
| 7237229 | Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration This invention makes debugging more efficient when an object program is intended for processing a loop made up of n groups of iteration-forming instructions. Instructions in the secondary assembler program each has a combination of a line number “;lx” and an ite... | 06/26/2007 |
| 7234136 | Method and apparatus for selecting references for prefetching in an optimizing compiler One embodiment of the present invention provides a system that generates code to perform anticipatory prefetching for data references. During operation, the system receives code to be executed on a computer system. Next, the system analyzes the code to identify data... | 06/19/2007 |
| 7225439 | Combining write-barriers within an inner loop with fixed step The present invention provides a technique for reducing the number of write barriers executed in mutator code without compromising garbage collector performance. To that end, when mutator instructions located within an inner-most nested loop (“inner loop”) modif... | 05/29/2007 |
| 7222218 | System and method for goal-based scheduling of blocks of code for concurrent execution A scheduler may be configured to schedule a plurality of blocks of concurrent code for multi-threaded execution. The scheduler may be configured to initiate multi-threaded execution of the blocks of concurrent code in an order determined by block-level performance c... | 05/22/2007 |
| 7222337 | System and method for range check elimination via iteration splitting in a dynamic compiler A range check elimination loop structure is provided. The range check elimination loop structure includes a pre-loop structure based on an original loop structure, where the pre-loop structure is capable of testing indexing expressions for underflow. In addition, a ... | 05/22/2007 |
| 7213130 | Instruction rollback processor system, an instruction rollback method and an instruction rollback program An instruction rollback processor system according to the present invention is provided. The instruction rollback processor system includes: an instruction window buffer storing a plurality of instructions not yet executed and are arranged in a predetermined order; ... | 05/01/2007 |
