Subclasses list- 1 CIRCUIT DESIGN
Patents: 2435 Patent Applications: 386 - 2 Optimization (e.g., redundancy, compaction)
Patents: 1951 Patent Applications: 441 - 3 Translation (e.g., conversion, equivalence)
Patents: 933 Patent Applications: 191 - 4 Testing or evaluating
Patents: 3496 Patent Applications: 890 - 5 Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)
Patents: 2638 Patent Applications: 936 - 6 Timing analysis (e.g., delay time, path delay, latch timing)
Patents: 2127 Patent Applications: 667 - 7 Partitioning (e.g., function block, ordering constraint)
Patents: 909 Patent Applications: 112 - 8 Floorplanning
Patents: 1407 Patent Applications: 275 - 9 Detailed placement (i.e., iterative improvement)
Patents: 813 Patent Applications: 178 - 10 Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)
Patents: 1465 Patent Applications: 500 - 11 Layout editor (e.g., updating)
Patents: 1278 Patent Applications: 346 - 12 Routing (e.g., routing map, netlisting)
Patents: 1388 Patent Applications: 373 - 13 Global routing (e.g., shortest path, dead space, or duplicate trace elimination)
Patents: 768 Patent Applications: 237 - 14 Detailed routing (e.g., channel routing, switch box routing)
Patents: 655 Patent Applications: 106 - 15 PCB wiring
Patents: 362 Patent Applications: 83 - 16 PLA, PLD, FPGA, OR MCM
Patents: 1209 Patent Applications: 128 - 17 Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)
Patents: 1157 Patent Applications: 188 - 18 Logical circuit synthesizer
Patents: 1744 Patent Applications: 357 - 19 DESIGN OF SEMICONDUCTOR MASK
Patents: 1502 Patent Applications: 602 - 20 Mesh generation
Patents: 395 Patent Applications: 106 - 21 Pattern exposure
Patents: 1136 Patent Applications: 478
| DefinitionGENERAL STATEMENT OF THE CLASS SUBJECT MATTER This class provides for electrical data processing apparatus and corresponding methods for the following subject matter: A. Processes or apparatus for sketching, designing, and analyzing circuit components. B. Processes or apparatus for planning, designing, analyzing, and devising a template used for etching circuit pattern on semiconductor wafers. SCOPE OF THE CLASS (1) Note. Processes and apparatus for the use of digital components in various types of digital logic circuitries or active electrical nonlinear circuits or devices are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (2) Note. Processes and apparatus for connections of electrical components on a printed circuit board are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (3) Note. Processes and apparatus for computer-controlled semiconductor fabrication are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (4) Note. Significantly claimed apparatus external to this class, claimed in combination with apparatus under the class definition, which perform data processing circuit design and analysis, are classified in the class appropriate to the external device unless specifically excluded therefrom. (5) Note. Nominally claimed apparatus external to this class in combination with apparatus under the class definition is classified in this class unless provided for in the appropriate external class. |
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