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| Number | Title | Issue Date |
| RE42294 | Semiconductor integrated circuit designing method and system using a design rule modification A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface a... | 04/12/2011 |
| 7908571 | Systems and media to improve manufacturability of semiconductor devices Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement an... | 03/15/2011 |
| 7904840 | Method and system to redistribute white space for minimizing wire length Disclosed are a method and a system for redistributing white space on an integrated circuit. The method comprises the steps of providing a series of circuit blocks for the integrated circuit, and placing the blocks on the integrated circuit to obtain a predefined op... | 03/08/2011 |
| 7900163 | Method and apparatus for identifying redundant scan elements An approach for producing optimized integrated circuit designs that support sequential flow partial scan testing may be embedded within an integrated circuit electronic design device. Using the approach, an integrated circuit design may be analyzed to identify and r... | 03/01/2011 |
| 7895539 | System for improving a logic circuit and associated methods A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a targe... | 02/22/2011 |
| 7890894 | Phase abstraction for formal verification A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the m... | 02/15/2011 |
| 7890895 | Determination of values of physical parameters of one or several components of an electronic circuit or of a microelectro-mechanical system A method for determining, for each of at least p physical parameters of one or several components of an electronic circuit or of a microelectromechanical system, a number n of experiment values of the physical parameter includes determining n vectors of dimension p,... | 02/15/2011 |
| 7886239 | Phase coherent differtial structures Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors. ... | 02/08/2011 |
| 7886238 | Visual yield analysis of intergrated circuit layouts Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net... | 02/08/2011 |
| 7882461 | Method for optimized automatic clock gating A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC d... | 02/01/2011 |
| 7882460 | Method of circuit power tuning through post-process flattening A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first optimization is subject to a first constraint that all instances of th... | 02/01/2011 |
| 7882456 | Optical lithography correction process A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-c... | 02/01/2011 |
| 7882458 | Power consumption analyzing method and computer-readable storage medium A power consumption analyzing method, to be implemented by a computer, is for a circuit developing procedure that makes a logic design of the circuit in an RTL design stage and inserts a gated clock with respect to the circuit in a subsequent logic synthesis stage. ... | 02/01/2011 |
| 7882459 | Method and system for reduction of AND/OR subexpressions in structural design representations A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, ... | 02/01/2011 |
| 7882457 | DSP design system level power estimation Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the syst... | 02/01/2011 |
| 7873923 | Power gating logic cones Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) b... | 01/18/2011 |
| 7870515 | System and method for improved hierarchical analysis of electronic circuits A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels a... | 01/11/2011 |
| 7865848 | Layout optimization using parameterized cells A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version ... | 01/04/2011 |
| 7856606 | Apparatus, method and program product for suppressing waviness of features to be printed using photolithographic systems A method for minimizing rippling of features when imaged on a surface of a substrate using a mask. The method includes the steps of determining a deviation between a first representation of the design and a second representation of an image of the design at each of ... | 12/21/2010 |
| 7853902 | Method for designing a circuit, particularly having an active component A method for designing a circuit, particularly having an active component, preferably a high-frequency circuit, wherein: (a) a plurality of load lines is determined at least approximately; (b) a course of a small-signal parameter along each load line is determined a... | 12/14/2010 |
| 7849423 | Method of verifying photomask data based on models of etch and lithography processes A photomask dataset corresponding to a target-pattern is verified by simulating a resist-pattern that will be formed in a resist layer by a lithography process, simulating an etched-pattern that will be etched in a layer by a plasma process wherein said simulation c... | 12/07/2010 |
| 7849422 | Efficient cell swapping system for leakage power reduction in a multi-threshold voltage process A method for designing an integrated circuit, comprising the steps of (A) calculating an efficiency value for each of a plurality of equivalent cells in the design; and (B) selecting a number of the plurality of equivalent cells based on the efficiency values. The e... | 12/07/2010 |
| 7844925 | System and method for power domain optimization A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the... | 11/30/2010 |
| 7844924 | Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis A device for logic synthesis that can be used to synthesize LUT logic circuit having intermediate outputs for multiple-output logic functions. The device includes means to store node table 8 storing Binary Decision Diagram for Characteristic Function (BDD_for... | 11/30/2010 |
| 7840918 | Method and apparatus for physical implementation of a power optimized circuit design In a method of optimizing power consumption in an integrated circuit, a physically implemented circuit design meeting at least one timing constraint is provided. A design block of the physically implemented circuit design having a high toggle rate pattern is identif... | 11/23/2010 |
| 7840919 | Resource mapping of functional areas on an integrated circuit The availability of device resources of an IC are quantified for a circuit design by building a representation of resource sites for the IC. Initial availability values are assigned to the resource sites, and any components having locking constraints are identified ... | 11/23/2010 |
| 7831937 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gat... | 11/09/2010 |
| 7823093 | Method and system for reduction of and/or subexpressions in structural design representations A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, ... | 10/26/2010 |
| 7818692 | Automated optimization of device structure during circuit design stage A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor dev... | 10/19/2010 |
| 7818694 | IC layout optimization to improve yield Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical a... | 10/19/2010 |
| 7818693 | Methodology for improving device performance prediction from effects of active area corner rounding A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which t... | 10/19/2010 |
| 7814443 | Graph-based pattern matching in L3GO designs A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a system for defining variable patterns using a pattern description language to create a glyph layout... | 10/12/2010 |
| 7810053 | Method and system of dynamic power cutoff for active leakage reduction in circuits The present invention relates to a novel active leakage power reduction technique, referred to as the dynamic power cutoff technique (DPCT). The DPCT method of the present invention can reduce active leakage, standby leakage, and dynamic power by applying the dynami... | 10/05/2010 |
| 7810054 | Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circu... | 10/05/2010 |
| 7802209 | Method for reducing timing libraries for intra-die model in statistical static timing analysis A method for performing statistical static timing analysis on an integrated circuit (IC) is disclosed, which comprises identifying a plurality of turned-on devices in the IC during a predetermined operation of the IC, choosing only the libraries of the plurality of ... | 09/21/2010 |
| 7797646 | Method for using mixed multi-Vt devices in a cell-based design A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshol... | 09/14/2010 |
| 7793236 | System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one o... | 09/07/2010 |
| 7793237 | System, structure and method of providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having... | 09/07/2010 |
| 7793238 | Method and apparatus for improving a circuit layout using a hierarchical layout description Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement o... | 09/07/2010 |
| 7788609 | Method and apparatus for optimizing an optical proximity correction model A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is d... | 08/31/2010 |
