Subclasses list

• 100 DATA PROCESSING SYSTEM ERROR OR FAULT HANDLING 
  Patents: 153
  Patent Applications: 75
• 1 Reliability and availability 
  Patents: 660
  Patent Applications: 148
• 2 Fault recovery 
  Patents: 923
  Patent Applications: 423
• 3 By masking or reconfiguration 
  Patents: 432
  Patent Applications: 136
• 4 Of network 
  Patents: 3037
  Patent Applications: 611
• 5 Of memory or peripheral subsystem 
  Patents: 1513
  Patent Applications: 408
• 6 Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data) 
  Patents: 3321
  Patent Applications: 665
• 7 Reconfiguration (e.g., adding a replacement storage component) 
  Patents: 1245
  Patent Applications: 100
• 8 Isolating failed storage location (e.g., sector remapping) 
  Patents: 754
  Patent Applications: 107
• 9 Access processor affected (e.g., I/O processor, MMU, DMA processor) 
  Patents: 316
  Patent Applications: 20
• 10 Of processor 
  Patents: 803
  Patent Applications: 83
• 11 Concurrent, redundantly operating processors 
  Patents: 1067
  Patent Applications: 116
• 12 Synchronization maintenance of processors 
  Patents: 443
  Patent Applications: 57
• 13 Prepared backup processor (e.g., initializing cold backup) or updating backup processor (e.g., by checkpoint message) 
  Patents: 875
  Patent Applications: 135
• 14 Of power supply 
  Patents: 367
  Patent Applications: 74
• 15 State recovery (i.e., process or data file) 
  Patents: 1342
  Patent Applications: 317
• 16 Forward recovery (e.g., redoing committed action) 
  Patents: 346
  Patent Applications: 72
• 17 Reexecuting single instruction or bus cycle 
  Patents: 136
  Patent Applications: 26
• 18 Transmission data record (e.g., for retransmission) 
  Patents: 298
  Patent Applications: 59
• 19 Undo record 
  Patents: 176
  Patent Applications: 44
• 20 Plural recovery data sets containing set interrelation data (e.g., time values or log record numbers) 
  Patents: 545
  Patent Applications: 39
• 21 State validity check 
  Patents: 172
  Patent Applications: 22
• 22 With power supply status monitoring 
  Patents: 470
  Patent Applications: 27
• 23 Resetting processor 
  Patents: 453
  Patent Applications: 46
• 24 Safe shutdown 
  Patents: 371
  Patent Applications: 33
• 25 Fault locating (i.e., diagnosis or testing) 
  Patents: 1766
  Patent Applications: 311
• 26 Artificial intelligence (e.g., diagnostic expert system) 
  Patents: 608
  Patent Applications: 131
• 27 Particular access structure 
  Patents: 418
  Patent Applications: 89
• 28 Substituted emulative component (e.g., emulator microprocessor) 
  Patents: 335
  Patent Applications: 24
• 29 Memory emulator feature 
  Patents: 114
  Patent Applications: 13
• 30 Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path) 
  Patents: 1361
  Patent Applications: 200
• 31 Additional processor for in-system fault locating (e.g., distributed diagnosis program) 
  Patents: 544
  Patent Applications: 49
• 32 Particular stimulus creation 
  Patents: 325
  Patent Applications: 137
• 33 Derived from analysis (e.g., of a specification or by stimulation) 
  Patents: 500
  Patent Applications: 72
• 34 Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping) 
  Patents: 391
  Patent Applications: 52
• 35 Substituted or added instruction (e.g., code instrumenting, breakpoint instruction) 
  Patents: 379
  Patent Applications: 59
• 36 Test sequence at power-up or initialization 
  Patents: 489
  Patent Applications: 93
• 37 Analysis (e.g., of output, state, or design) 
  Patents: 897
  Patent Applications: 383
• 38 Of computer software 
  Patents: 2460
  Patent Applications: 591
• 39 Monitor recognizes sequence of events (e.g., protocol or logic state analyzer) 
  Patents: 817
  Patent Applications: 152
• 40 Component dependent technique 
  Patents: 174
  Patent Applications: 34
• 41 For reliability enhancing component (e.g., testing backup spare, or fault injection) 
  Patents: 239
  Patent Applications: 13
• 42 Memory or storage device component fault 
  Patents: 1138
  Patent Applications: 222
• 43 Bus, I/O channel, or network path component fault 
  Patents: 1355
  Patent Applications: 155
• 44 Peripheral device component fault 
  Patents: 337
  Patent Applications: 24
• 45 Output recording (e.g., signature or trace) 
  Patents: 851
  Patent Applications: 249
• 46 Operator interface for diagnosing or testing 
  Patents: 697
  Patent Applications: 76
• 47 Performance monitoring for fault avoidance 
  Patents: 1793
  Patent Applications: 322
• 48 Error detection or notification 
  Patents: 1560
  Patent Applications: 511
• 49 State error (i.e., content of instruction, data, or message) 
  Patents: 431
  Patent Applications: 171
• 50 State out of sequence 
  Patents: 101
  Patent Applications: 6
• 51 Control flow state sequence monitored (e.g., watchdog processor for control-flow checking) 
  Patents: 201
  Patent Applications: 16
• 52 Error checking code 
  Patents: 352
  Patent Applications: 46
• 53 Address error 
  Patents: 197
  Patent Applications: 17
• 54 Storage content error 
  Patents: 415
  Patent Applications: 129
• 55 Timing error (e.g., watchdog timer time-out) 
  Patents: 538
  Patent Applications: 66
• 56 Bus or I/O channel device fault 
  Patents: 261
  Patent Applications: 31
• 57 Error forwarding and presentation (e.g., operator console, error display) 
  Patents: 618
  Patent Applications: 330
• 699 PULSE OR DATA ERROR HANDLING 
  Patents: 64
  Patent Applications: 58
• 700 Skew detection correction 
  Patents: 500
  Patent Applications: 94
• 701 Data formatting to improve error detection correction capability 
  Patents: 704
  Patent Applications: 104
• 702 Memory access (e.g., address permutation) 
  Patents: 240
  Patent Applications: 21
• 703 Testing of error-check system 
  Patents: 269
  Patent Applications: 13
• 704 Error count or rate 
  Patents: 941
  Patent Applications: 203
• 705 Pseudo-error rate 
  Patents: 56
  Patent Applications: 3
• 706 Up-down counter 
  Patents: 63
  Patent Applications: 0
• 707 Synchronization control 
  Patents: 167
  Patent Applications: 7
• 708 Shutdown or establishing system parameter (e.g., transmission rate) 
  Patents: 324
  Patent Applications: 21
• 709 Data pulse evaluation/bit decision 
  Patents: 169
  Patent Applications: 10
• 710 Replacement of memory spare location, portion, or segment 
  Patents: 809
  Patent Applications: 101
• 711 Spare row or column 
  Patents: 370
  Patent Applications: 14
• 712 Transmission facility testing 
  Patents: 750
  Patent Applications: 62
• 713 For channel having repeater 
  Patents: 68
  Patent Applications: 3
• 714 By tone signal 
  Patents: 47
  Patent Applications: 3
• 715 Test pattern with comparison 
  Patents: 312
  Patent Applications: 25
• 716 Loop-back 
  Patents: 236
  Patent Applications: 11
• 717 Loop or ring configuration 
  Patents: 134
  Patent Applications: 5
• 718 Memory testing 
  Patents: 2348
  Patent Applications: 519
• 719 Read-in with read-out and compare 
  Patents: 841
  Patent Applications: 112
• 720 Special test pattern (e.g., checkerboard, walking ones) 
  Patents: 313
  Patent Applications: 24
• 721 Electrical parameter (e.g., threshold voltage) 
  Patents: 292
  Patent Applications: 54
• 722 Performing arithmetic function on memory contents 
  Patents: 86
  Patent Applications: 12
• 723 Error mapping or logging 
  Patents: 512
  Patent Applications: 67
• 724 Digital logic testing 
  Patents: 2631
  Patent Applications: 529
• 725 Programmable logic array (PLA) testing 
  Patents: 460
  Patent Applications: 18
• 726 Scan path testing (e.g., level sensitive scan design (LSSD)) 
  Patents: 1579
  Patent Applications: 463
• 727 Boundary scan 
  Patents: 905
  Patent Applications: 175
• 728 Random pattern generation (includes pseudorandom pattern) 
  Patents: 193
  Patent Applications: 41
• 729 Plural scan paths 
  Patents: 468
  Patent Applications: 124
• 730 Addressing 
  Patents: 97
  Patent Applications: 6
• 731 Clock or synchronization 
  Patents: 541
  Patent Applications: 209
• 732 Signature analysis 
  Patents: 400
  Patent Applications: 48
• 733 Built-in testing circuit (BILBO) 
  Patents: 1481
  Patent Applications: 256
• 734 Structural (in-circuit test) 
  Patents: 544
  Patent Applications: 42
• 735 Device response compared to input pattern 
  Patents: 319
  Patent Applications: 36
• 736 Device response compared to expected fault-free response 
  Patents: 913
  Patent Applications: 67
• 737 Device response compared to fault dictionary/truth table 
  Patents: 109
  Patent Applications: 7
• 738 Including test pattern generator 
  Patents: 1203
  Patent Applications: 192
• 739 Random pattern generation (includes pseudorandom pattern) 
  Patents: 321
  Patent Applications: 20
• 740 Having analog signal 
  Patents: 102
  Patent Applications: 6
• 741 Simulation 
  Patents: 353
  Patent Applications: 64
• 742 Testing specific device 
  Patents: 293
  Patent Applications: 133
• 743 Addressing 
  Patents: 162
  Patent Applications: 5
• 744 Clock or synchronization 
  Patents: 468
  Patent Applications: 47
• 745 Determination of marginal operation limits 
  Patents: 233
  Patent Applications: 14
• 746 Digital data error correction 
  Patents: 834
  Patent Applications: 403
• 747 Substitution of previous valid data 
  Patents: 236
  Patent Applications: 29
• 748 Request for retransmission 
  Patents: 1014
  Patent Applications: 682
• 749 Retransmission if no ACK returned 
  Patents: 429
  Patent Applications: 225
• 750 Feedback to transmitter for comparison 
  Patents: 124
  Patent Applications: 28
• 751 Including forward error correction capability 
  Patents: 414
  Patent Applications: 99
• 752 Forward correction by block code 
  Patents: 1112
  Patent Applications: 936
• 753 Double error correcting with single error correcting code 
  Patents: 105
  Patent Applications: 16
• 754 Error correction during refresh cycle 
  Patents: 70
  Patent Applications: 7
• 755 Double encoding codes (e.g., product, concatenated) 
  Patents: 1402
  Patent Applications: 394
• 756 Cross-interleave Reed-Solomon code (CIRC) 
  Patents: 282
  Patent Applications: 27
• 757 Parallel generation of check bits 
  Patents: 211
  Patent Applications: 25
• 758 Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity) 
  Patents: 1372
  Patent Applications: 760
• 759 Look-up table encoding or decoding 
  Patents: 210
  Patent Applications: 26
• 760 Threshold decoding (e.g., majority logic) 
  Patents: 63
  Patent Applications: 27
• 761 Random and burst error correction 
  Patents: 236
  Patent Applications: 5
• 762 Burst error correction 
  Patents: 389
  Patent Applications: 48
• 763 Memory access 
  Patents: 922
  Patent Applications: 545
• 764 Error correct and restore 
  Patents: 369
  Patent Applications: 81
• 765 Error pointer 
  Patents: 168
  Patent Applications: 12
• 766 Check bits stored in separate area of memory 
  Patents: 362
  Patent Applications: 44
• 767 Code word for plural n-bit (n>1) storage units (e.g., x4 DRAM's) 
  Patents: 130
  Patent Applications: 14
• 768 Error correction code for memory address 
  Patents: 173
  Patent Applications: 49
• 769 Dynamic data storage 
  Patents: 522
  Patent Applications: 57
• 770 Disk array 
  Patents: 264
  Patent Applications: 49
• 771 Tape 
  Patents: 83
  Patent Applications: 6
• 772 Code word parallel access 
  Patents: 59
  Patent Applications: 2
• 773 Solid state memory 
  Patents: 254
  Patent Applications: 150
• 774 Adaptive error-correcting capability 
  Patents: 555
  Patent Applications: 51
• 775 Synchronization 
  Patents: 297
  Patent Applications: 17
• 776 For packet or frame multiplexed data 
  Patents: 630
  Patent Applications: 329
• 777 Hamming code 
  Patents: 124
  Patent Applications: 76
• 778 Nonbinary data (e.g., ternary) 
  Patents: 54
  Patent Applications: 1
• 779 Variable length data 
  Patents: 103
  Patent Applications: 10
• 780 Using symbol reliability information (e.g., soft decision) 
  Patents: 325
  Patent Applications: 111
• 781 Code based on generator polynomial 
  Patents: 495
  Patent Applications: 116
• 782 Bose-Chaudhuri-Hocquenghem code 
  Patents: 147
  Patent Applications: 80
• 783 Golay code 
  Patents: 34
  Patent Applications: 15
• 784 Reed-Solomon code 
  Patents: 617
  Patent Applications: 213
• 785 Syndrome computed 
  Patents: 434
  Patent Applications: 125
• 786 Forward error correction by tree code (e.g., convolutional) 
  Patents: 729
  Patent Applications: 99
• 787 Random and burst errors 
  Patents: 85
  Patent Applications: 0
• 788 Burst error 
  Patents: 172
  Patent Applications: 3
• 789 Synchronization 
  Patents: 150
  Patent Applications: 6
• 790 Puncturing 
  Patents: 309
  Patent Applications: 74
• 791 Sequential decoder (e.g., Fano or stack algorithm) 
  Patents: 54
  Patent Applications: 5
• 792 Trellis code 
  Patents: 607
  Patent Applications: 106
• 793 Syndrome decodable (e.g., self orthogonal) 
  Patents: 83
  Patent Applications: 8
• 794 Maximum likelihood 
  Patents: 571
  Patent Applications: 69
• 795 Viterbi decoding 
  Patents: 1006
  Patent Applications: 152
• 796 Branch metric calculation 
  Patents: 411
  Patent Applications: 49
• 797 Majority decision/voter circuit 
  Patents: 292
  Patent Applications: 15
• 798 Error detection for synchronization control 
  Patents: 413
  Patent Applications: 32
• 799 Error/fault detection technique 
  Patents: 480
  Patent Applications: 239
• 800 Parity bit 
  Patents: 567
  Patent Applications: 127
• 801 Parity generator or checker circuit detail 
  Patents: 288
  Patent Applications: 133
• 802 Even and odd parity 
  Patents: 67
  Patent Applications: 1
• 803 Parity prediction 
  Patents: 35
  Patent Applications: 5
• 804 Plural dimension parity check 
  Patents: 121
  Patent Applications: 10
• 805 Storage accessing (e.g., address parity check) 
  Patents: 440
  Patent Applications: 28
• 806 Constant-ratio code (m/n) 
  Patents: 31
  Patent Applications: 5
• 807 Check character 
  Patents: 402
  Patent Applications: 250
• 808 Modulo-n residue check character 
  Patents: 56
  Patent Applications: 5
• 809 Code constraint monitored 
  Patents: 89
  Patent Applications: 7
• 810 Multilevel coding (n>2) 
  Patents: 61
  Patent Applications: 1
• 811 Forbidden combination or improper condition 
  Patents: 157
  Patent Applications: 9
• 812 Specified digital signal or pulse count 
  Patents: 101
  Patent Applications: 2
• 813 Two key-down detector 
  Patents: 11
  Patent Applications: 0
• 814 Data timing/clocking 
  Patents: 241
  Patent Applications: 2
• 815 Time delay/interval monitored 
  Patents: 225
  Patent Applications: 1
• 816 Two-rail logic 
  Patents: 23
  Patent Applications: 0
• 817 Noise level 
  Patents: 26
  Patent Applications: 3
• 818 Missing-bit/drop-out detection 
  Patents: 53
  Patent Applications: 1
• 819 Comparison of data 
  Patents: 403
  Patent Applications: 93
• 820 Plural parallel devices of channels 
  Patents: 212
  Patent Applications: 8
• 821 Transmission facility 
  Patents: 142
  Patent Applications: 6
• 822 Sequential repetition 
  Patents: 150
  Patent Applications: 3
• 823 True and complement data 
  Patents: 54
  Patent Applications: 5
• 824 Device output compared to input 
  Patents: 81
  Patent Applications: 4