Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Number | Title | Issue Date |
| 7930623 | Method and system for generating parallel codes A method for generating parallel codes is provided that includes generating a plurality of pairs of outputs for each clock cycle using a single code generator and generating a code based on each pair of outputs using the single code generator. ... | 04/19/2011 |
| 7433793 | Error detection apparatus and method and signal extractor A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through th... | 10/07/2008 |
| 7421565 | Method and apparatus for indirectly addressed vector load-add -store across multi-processors A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 09/02/2008 |
| 7376889 | Memory device capable of detecting its failure A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data inp... | 05/20/2008 |
| 7366873 | Indirectly addressed vector load-operate-store method and apparatus A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 04/29/2008 |
| 7334182 | Serial data preservation method A timer circuit for tracking an elapsed time of an electronic device is provided. The timer circuit compares differences in elapsed times written to memory addresses of a memory chip with a periodic interval to determine whether any elapsed times written to the memo... | 02/19/2008 |
| 7330993 | Slew rate control mechanism According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate base... | 02/12/2008 |
| 7151806 | Time code signal transmitting method and time code signal transmitting apparatus The present invention comprises the step of reading a check-receiving data included in a transmitted time code signal and using the read check-receiving data to generate a transmitting side checking data, and the step of attaching the transmitting side checking data... | 12/19/2006 |
| 7069494 | Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a pl... | 06/27/2006 |
| 7013413 | Method for compressing output data and a packet command driving type memory device The present invention relates to a packet command driving type memory device, a method for compressing output data according to the present invention is characterized to write first data of a certain bit in a corresponding address of core cell regions, read the firs... | 03/14/2006 |
| 6938201 | Error detection system for a FIFO memory An error detection system for detecting errors in data output from a FIFO memory includes a first CRC generator for receiving an inbound data stream and generating a first CRC value based on a data block in the inbound data stream. A device coupled to the first CRC ... | 08/30/2005 |
| 6914447 | High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments The present invention pertains to radiation sources that mimic radiation environment(s) encountered by packaged semiconductor devices. The sources are suitable for use in test systems operative to test for soft error and/or failure rates in devices sensitive to such... | 07/05/2005 |
| 6816988 | Method and system for minimal-time bit-error-rate testing A bit-error rate is tested in a minimal necessary time period. A block of bits is measured and a cumulative number of bit errors is counted in parallel with calculation of a posterior cumulative distribution function. The posterior cumulative distribution function p... | 11/09/2004 |
| 6614847 | Content-based video compression A video compression method and system including object-oriented compression plus error correction using decoder feedback.... | 09/02/2003 |
| 6601007 | Method and system to increase the performance of high-speed backplanes A circuit board, for use with a high speed backplane, includes transmitter and receiver with circuitry for correcting for multipath signal errors. A training sequence that is often a pseudo-random signal is transmitted by the transmitter on a first circui... | 07/29/2003 |
| 6584577 | System for measuring response time of a circuit by determining the time difference between the earlier and the later clock pulses applied to the circuit A method and device for measuring the response time of a circuit are described in which clocking pulses are applied to the circuit at input pads, the input pads being connected to the circuit by circuitry having substantially the same delays. By adjusting... | 06/24/2003 |
| 6505310 | Connection integrity monitor for digital selection circuits A circuit connection integrity monitor detecting and isolating connection faults in data path cards is disclosed. A connection integrity monitoring method and corresponding apparatus are applicable to selector and cross-connect circuits and permit a user ... | 01/07/2003 |
| 6345371 | Method of performing diagnostic procedures on a queue structure A method and apparatus are disclosed for testing the functionality of a queue structure. An input circuit is provided for inputting data into an input portion of the queue structure, while an output circuit is provided for retrieving data from an output p... | 02/05/2002 |
| 6321283 | Method and apparatus for determining a data transmission capacity between communicatively connected source and target devices The field of the present invention is related to the transmission of data between a source device and a target device. More particularly, the present invention relates to the determination of a capacity limitation associated with the communication connect... | 11/20/2001 |
| 6301685 | Error propagation path extraction system, error propagation path extraction method, and recording medium recording error propagation path extraction control program To realize high-speed error propagation path extraction in a combinational circuit, a logical contradiction judgment section detects the logical state of each signal line under the implication by a first implication section and judges whether the logical ... | 10/09/2001 |
| 6208647 | Multicast extension to data link layer protocols A data link layer switch includes a switching mechanism coupled to several port interface controllers. The port interface controllers include an address table, an address learner, and an address matcher. The address table stores multicast addresses for ho... | 03/27/2001 |
| 6154861 | Method and apparatus for built-in self-test of smart memories A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any fail... | 11/28/2000 |
| 5961658 | PR4 equalization and an EPR4 remod/demod sequence detector in a sampled amplitude read channel A sampled amplitude read channel is disclosed for disk storage systems that employs an EPR4 remod/demod sequence detector. To reduce the complexity of timing recovery, gain control and adaptive equalization, the channel samples are initially equalized int... | 10/05/1999 |
| 5938790 | Sequence error event detection and correction using fixed block digital sum codes A data receiving channel has a signal converter that converts a received signal into a digital signal. The digital signal is then applied to a Viterbi detector that will provide, as an output, a stream of digital signals that have a maximum likelihood of ... | 08/17/1999 |
| 5931966 | Viterbi detector with a pipelined look-up table of squared errors The present invention is directed to a detector circuit for detecting a binary data sequence from an input sequence of data. The detector circuit comprises a storage device for storing a plurality of values which correspond to the squared errors computed ... | 08/03/1999 |
| 5920489 | Method and system for modeling the behavior of a circuit A method and system for modeling the behavior of a circuit are disclosed. A list specifying a plurality of transistors within the circuit and interconnections between the plurality of transistors is provided. Each fan node within the circuit is identified... | 07/06/1999 |
| 5896176 | Content-based video compression A video compression method and system including object-oriented compression plus error correction using decoder feedback.... | 04/20/1999 |
| 5887197 | Apparatus for image data to be displayed by transferring only data which is determined to be valid after shifting the data over a range of given length A data transfer system is provided for use in shifting and transferring image data and the like, wherein the amount of shift, the horizontal size and the like of data to be shifted are held in a dedicated circuit which is connected between a CPU and a mem... | 03/23/1999 |
| 5715238 | Apparatus and method for detecting a loss of a telecommunications channel connection An apparatus and method are provided for a data communications device (100), such as a modem, to detect the loss of a telecommunications channel connection, in the absence of other notification signals. The apparatus and method embodiments of the inventio... | 02/03/1998 |
| 5586204 | Integrity checking procedure for high throughput data transformations Integrity checking apparatus and procedures for checking safety-critical high throughput data and image transformations. The present invention randomly samples input and output data streams and uses the sampled data in either a forward or backward transfo... | 12/17/1996 |
| 5572679 | Multiprocessor system transferring abnormality detection signal generated in networking apparatus back to processor in parallel with data transfer route A multiprocessor system comprising a networking apparatus and a plurality of data processing apparatuses for transferring data through the networking apparatus from one to another of the plurality of data processing apparatuses. The networking apparatus c... | 11/05/1996 |
| 5537663 | System for determining configuration of devices installed on a computer bus by comparing response time of data lines to read from I/O address when undriven In a system that executes the method according to the invention, each slot on the system bus is individually enabled at start-up and each address of an address range is read to determine whether an expansion board is installed in the slot and is respondin... | 07/16/1996 |
| 5490266 | Process oriented logic simulation having stability checking A logic simulator for optimal configurability of combinatorial and sequential logic circuits in a simulated behavioral form. The present invention contains process oriented functional blocks with event posting to eliminate unnecessary evaluations in logic... | 02/06/1996 |
| 5381418 | Testable latch self checker The present invention operates by verifying correct latch operation in a digital circuit. After a value has been stored in a latch, electronic circuitry can verify that the value has been stored correctly. The electronic circuitry that performs this verif... | 01/10/1995 |
| 5379413 | User selectable word/byte input architecture for flash EEPROM memory write and erase operations A circuit for accessing data which may be stored in a flash EEPROM memory array in sixteen bit quantities has apparatus for writing data to the array in eight bit quantities which quantities may be either the lower or upper byte of a word and appear at id... | 01/03/1995 |
| 5287476 | Personal computer system with storage controller controlling data transfer This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices suc... | 02/15/1994 |
| 5272705 | Semiconductor integrated circuit device A P-to-S shift register (61) includes nine R-S-FFs (70-78) serially connected. At the H level rising edge of a P-to-S shift register clock (T2), latch data of the FFs (70-77) are shifted rightwardly to their adjacent FFs (71-78), whereby a serial data (D1... | 12/21/1993 |
| 5260906 | Semiconductor memory having built-in test circuit A semiconductor memory comprises memory cell arrays and data amplifiers, four or more respectively, and two common read buses for them. Each data amplifier outputs the first and second data having respective levels complementary to each other. It further ... | 11/09/1993 |
| 5241550 | System for accurately confirming cross-connection in a cross-connection network On confirming whether or not a matrix switch correctly carries out cross-connection between input and output terminals of the switch in accordance with connection information signals memorized in a memory included in a controller, a cross-connection confi... | 08/31/1993 |
| 5216697 | Signal quality detector circuit A signal quality detector circuit which detects an error signal of an input signal, used for detecting transmission quality of a transmission line. The detector circuit equalizes the input baseband signal, analog-to-digital-converts the equalized signal t... | 06/01/1993 |
