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| Number | Title | Issue Date |
| 8181101 | Data bus system, its encoder/decoder and encoding/decoding method The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data accor... | 05/15/2012 |
| 8032819 | CSA 5-3 compressor circuit and carry-save adder circuit using same At least two Exclusive-OR (EOR) circuits for carry-out which output carry-out bits and the complementary signals thereof are provided in the 5-3 compressor circuits constituted by an Exclusive-OR (EOR) circuit group, and dual lanes are employed at least for carry-ou... | 10/04/2011 |
| 7571379 | Method and system for configuring registers in microcontrollers, and corresponding computer-program product A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes... | 08/04/2009 |
| 7546519 | Method and apparatus for detecting and correcting soft-error upsets in latches An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic nodes always discharges when the clock signal transitions from an active ... | 06/09/2009 |
| 7426686 | System and method for verifying data integrity A system for verifying data integrity includes a central processing unit (CPU) (1), a non-volatile random access memory (NVRAM) (2), and a program memory (3). The NVRAM includes: a plurality of data blocks (23), each data block including ... | 09/16/2008 |
| 7392465 | Testing ram address decoder for resistive open defects Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types o... | 06/24/2008 |
| 7336102 | Error correcting logic system The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redu... | 02/26/2008 |
| 7302631 | Low overhead coding techniques A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a ... | 11/27/2007 |
| 7180850 | Frequency offset differential pulse position modulation The present invention provides such a need by utilizing a frequency offset differential pulse position modulation scheme to transmit data between computing devices within a wireless network system. The differential pulse position modulation component of the scheme e... | 02/20/2007 |
| 7149956 | Converging error-recovery for multi-bit-incrementing gray code An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, ... | 12/12/2006 |
| 7113435 | Data compression read mode for memory testing Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indicati... | 09/26/2006 |
| 7030731 | Wireless identification systems and protocols Monitoring systems and protocols are disclosed that are flexible in mode operation and format depending on the environment in which they are used. Such monitoring systems and protocols are able to change their utilization automatically, or by received instruction to... | 04/18/2006 |
| 6907090 | Method and apparatus to recover data from pulses Methods and corresponding apparatus to recover data from a signal comprising groups of pulses generated in response to analog waveforms are described. Data recovery in accordance with the invention is based on parameters characterizing the groups of pulses. These pa... | 06/14/2005 |
| 6799291 | Method and system for detecting a hard failure in a memory array A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a fir... | 09/28/2004 |
| 6690733 | Method for data transmission In a method for data transmission in which the binary original data (D0, . . . , Dm) is transferred from a transmitter to a unit of a receiver (1), selected preferably by means of a binary base address (A0, . . . , An), preferably to a register (80, . . .... | 02/10/2004 |
| 6507929 | System and method for diagnosing and repairing errors in complementary logic A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a c... | 01/14/2003 |
| 6502220 | Complementary logic error detection and correction A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to... | 12/31/2002 |
| 6253350 | Method and system for detecting errors within complementary logic circuits A method and system for detecting faults within dual-rail complementary logic circuits. A method and system are disclosed for detecting faults within dual-rail complementary logic circuits. A dual-rail complementary logic circuit is coupled to an associat... | 06/26/2001 |
| 5903613 | Data reception device, data reception method and electronic equipment The invention relates to a data reception device for receiving packetized data in the form of a differential signal. This device comprises a data reception section that generates a digital signal an the basis of the differential signal; a decode section t... | 05/11/1999 |
| 5894487 | Error detection of directory arrays in dynamic circuits A system and method for providing error detection in a directory has been disclosed. The method and system include comparing a first group of data and a second group of data to provide a comparison signal and detecting errors in response to the comparison... | 04/13/1999 |
| 5881078 | Logic circuit having error detection function and processor including the logic circuit Soft errors generated at an active time are reduced by adding a small-scale circuit to a high performance LSI, such as a processor without reducing the performance of the circuit. The processor has individual logic circuits each having a plurality of stag... | 03/09/1999 |
| 5838696 | Record carrier and devices for reading and recording such a record carrier A record carrier has recorded thereon a data signal which represents data words, added codewords of a first type and added codewords of a second type. The added codewords of the first type have a predefined first relation to the data words, and the added ... | 11/17/1998 |
| 5822514 | Method and device for processing signals in a protection system A method and system for processing signals in a protection system involves executing operations on signals that are complimentary to each other, such that the results of the operations determines whether the operations can be continued. Logic operations a... | 10/13/1998 |
| 5701410 | Method and system for detecting fault conditions on multiplexed networks A method for detecting fault conditions on a multiplexed network having first and second busses. The method includes sensing a start of frame delimiter (SOF) for the first bus, and determining the state of the second bus when the SOF is sensed. If the sta... | 12/23/1997 |
| 5666381 | Communication system used in semiconductor device manufacturing equipment A communication system used in a semiconductor device manufacturing equipment includes a master side transmission unit having a master transmitting logic module for transmitting information in an inverted two-successive transmission mode in which informat... | 09/09/1997 |
| 5555438 | Method for synchronously transferring serial data to and from an input/output (I/O) module with true and complement error detection coding An industrial controller Input/Output module includes on-board processing circuitry in the form of a microprocessor and associated memory, a first programmable logic circuit and a second programmable logic circuit connected through an isolation interface.... | 09/10/1996 |
| 5404374 | Method and apparatus for transmitting and receiving encoded data using multiple frequency coding In a communication system including a plurality of networked stations that communicate using a slow frequency hopping system, a method for encoding a packet of data in a transmitting station and decoding the data in a receiving station. In the transmittin... | 04/04/1995 |
| 5394410 | Differentially coded and guard pulse position modulation for communication networks In a wireless infrared communications system, a technique for encoding data for serial transmission and the correlative technique for decoding the transmitted data. A data transmission period is divided into a plurality of slots. In a given pair of slots,... | 02/28/1995 |
| 5325376 | Communication system for detecting a communication error in information transmitted between a plurality of units and a main control unit A communication system includes a main control unit controlling a plurality of units, a transmitter for transmitting information between the main control unit and the plurality of units, and an error detector. The error detector can include a modulator an... | 06/28/1994 |
| 5311524 | Fault tolerant three port communications module A fault tolerant three port communications module has two control ports for receiving commands from two computers, and a communications port for transferring data over a communications channel in response to the commands. Each control port includes a sele... | 05/10/1994 |
| 5241549 | Data communications system A train of signals is generated by clocking an 8-bit word from an 8-bit shift register which has been loaded with an initial data word. The register is provided with feedback loop. The serial data is supplied along a communication link to a similar or ide... | 08/31/1993 |
| 5224107 | Method in a parallel test apparatus for semiconductor memories A method in a parallel test apparatus provides for parallel testing a plurality of memory cells of a semiconductor module in parallel. The information read from the memory cells that are forwarded via the parallel test apparatus are tested to determine wh... | 06/29/1993 |
| 5193177 | Fault indicating microcomputer interface units A microcomputer interface arrangement includes a microcomputer having I/O ports coupled to individual interface units. A fault detection circuit detects a fault in an interface unit, interrupts the microcomputer and inverts the input state of the faulty u... | 03/09/1993 |
| 5168510 | Spread spectrum-time diversity communications systems and transceivers for multidrop area networks Messages are transmitted on pairs of frequencies that are orthogonal, that is the frequencies have no least common denominator (are prime to each other). A message is transmitted on the first of the pair of frequencies and, simultaneously, its complement ... | 12/01/1992 |
| 4860286 | Encoding method in transmission of plurality of oversampled data channels, and apparatus for carrying out the method An encoding method in transmitting a plurality of parallel, independent and asynchronous data channels, each of which after encoding into serial from is to be supplied to an optical transmitter before transmission over a fibre-optic cable. The parallel da... | 08/22/1989 |
| 4785453 | High level self-checking intelligent I/O controller The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ("DMA"), a... | 11/15/1988 |
| 4750165 | Method of duplex data transmission using a send-and-wait protocol The invention provides a method of communicating data between a pair of transceivers in a full-duplex manner using a send-and-wait data handling protocol. The transceivers are connected by a pair of communication paths and each transceiver is adapted to s... | 06/07/1988 |
| 4740972 | Vital processing system adapted for the continuous verification of vital outputs from a railway signaling and control system Continuous verification of vital (fail-safe) outputs from an information processing system is obtained without the need for large computing capacity (overhead). Multibit test sequences are provided continuously during successive subparts of the processor ... | 04/26/1988 |
| 4712213 | Flip status line Fault checking of slave devices. All the slave devices are polled periodically by a master control circuit and their reponse is noted. The master control circuit asserts a control signal for every other poll so as to cause the slave device to invert the b... | 12/08/1987 |
| 4633473 | Fault tolerant communications interface A communications interface exchanges serial bit signals between sources differentially, over redundant, two conductor, primary and secondary channels. The primary channel provides the communications link during normal operation, and is monitored to ensure... | 12/30/1986 |
