Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 8190984 | Memory and method for checking reading errors thereof A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binar... | 05/29/2012 |
| 8181100 | Memory fault injection Techniques, apparatus, and systems for injecting a memory fault can include obtaining first data and second data different from the first data, generating first error detection information based on the first data, writing the second data to a memory unit using a spe... | 05/15/2012 |
| 8176407 | Comparing values of a bounded domain Methods, systems, and computer-readable media to compare values of a bounded domain are disclosed. A particular method includes, for each value in a bounded domain, determining a corresponding set of allowable errors associated with the value. The sets of allowable ... | 05/08/2012 |
| 8176406 | Hard error detection An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that referen... | 05/08/2012 |
| 8145988 | Command line testing Provided are a system, method and article of manufacture for validating an expected data output of an application under test. A first table comprising named columns populated with the expected data output and a second table comprising named columns associated with t... | 03/27/2012 |
| 8091014 | Electronic apparatus in which functioning of a microcomputer is monitored by another microcomputer to detect abnormal operation In an electronic apparatus, a first microcomputer is monitored by a second microcomputer, which periodically transmits data relating to a main function to the first microcomputer to be processed. The first microcomputer periodically updates a variable value, perform... | 01/03/2012 |
| 8055991 | Error detection and recovery using an asynchronous transaction journal Illustrative embodiments provide a computer implemented method, an apparatus, and a computer program product for error detection and recovery using an asynchronous transaction journal. In an illustrative embodiment the computer implemented method receives a request ... | 11/08/2011 |
| 8051368 | Microprocessor and method for detecting faults therein A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches a... | 11/01/2011 |
| 7992077 | Data slicer having an error correction device A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by addin... | 08/02/2011 |
| 7958439 | Defective memory block remapping method and system, and memory device and processor-based system using same A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses... | 06/07/2011 |
| 7870473 | Error detection device for an address decoder, and device for error detection for an address decoder An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated addr... | 01/11/2011 |
| 7836387 | System and method for protecting data across protection domain boundaries A system and method for ensuring or verifying the integrity of data transmitted between protection domains. When the data is transmitted, it may be received in a different logical configuration (e.g., as a different number of “chunks”). The receiving domain comp... | 11/16/2010 |
| 7802173 | Method to decode a data string The invention relates to decode data transmitted via US National Weather Service NOAA Weather Radio (NWR) transmitters or any other data transmitted in a comparable way. According to the invention a method to decode a received data string comprises the steps of loca... | 09/21/2010 |
| 7752533 | Systems and methods for improving radio frequency signal reception A demodulator cancels out the echo signal properties in the received signal to generate a primary signal, and cancels out the primary signal properties in the received signal to generate a separate echo signal. In addition, the demodulator may combine the primary si... | 07/06/2010 |
| 7747935 | Method and device for securing the reading of a memory A method reads a datum saved in a memory by selecting an address of the memory in which the datum to be read is saved, reading the datum in the memory at the selected address, saving the datum read in a storage space, and when the memory is not being accessed by a C... | 06/29/2010 |
| 7644349 | Interface circuit An interface circuit comprises at least one supply input and at least one data input with a protective circuit coupled between the at least one supply input and the at least one data input. A power supply circuit is coupled to the at least one supply input. The inte... | 01/05/2010 |
| 7596744 | Auto recovery from volatile soft error upsets (SEUs) In one embodiment, a programmable logic device for recovery from soft error upsets (SEUs) includes: a configuration memory operable to store configuration data; a configuration engine operable to configure the configuration memory; an error detection circuit operabl... | 09/29/2009 |
| 7587663 | Fault detection using redundant virtual machines A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system. ... | 09/08/2009 |
| 7587662 | Detection of noise within an operating frequency on a network Noise is detected within an operating frequency of a communication medium. Messages are monitored on the communication medium for corrupted messages. A noise detected signal is generated when a number of corrupted messages detected reaches a corrupted message thresh... | 09/08/2009 |
| 7559013 | Error detecting device, error detection method and control system An error detecting device enables proper detection of an occurrence of a data error in a register. The error detecting device for detecting an occurrence of a data error in a register for holding input data with reception of a write permission comprises an operation... | 07/07/2009 |
| 7543222 | System and method for checking BIOS ROM data A system for checking basic input output system read only memory (BIOS ROM) data includes a keyboard, a display, a computer host, and a checking device. The computer host has a BIOS ROM installed therein. The checking device includes: a data dividing module for divi... | 06/02/2009 |
| 7516395 | Memory checking apparatus and method Image or other data is stored in a memory. A first validation parameter (e.g., a checksum) is determined for the data stored in the memory at a first time, and stored. A second validation parameter is determined for the data stored in the memory at a second time, an... | 04/07/2009 |
| 7506241 | Method and apparatus for a self healing agent A method, apparatus, and computer instructions for managing a program. Operation of the program is monitored by an agent process. An observed operation of the program is compared with an expected operation of the program to form a comparison. A determination is made... | 03/17/2009 |
| 7458012 | Method for detecting code error A method for detecting a code error is proposed. The method is mainly applied for detecting whether there is a code error existed in the accessed data, in other words, for detecting whether there is only an error bit existed in the accessed data. After the data are ... | 11/25/2008 |
| 7444544 | Write filter cache method and apparatus for protecting the microprocessor core from soft errors A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write fi... | 10/28/2008 |
| 7444561 | Verifier for remotely verifying integrity of memory and method thereof A verifier for remotely checking integrity of a device connected via a network, includes a calculator which fills free areas in a memory of the device with random numbers and generates a local check code; an interface which transmits integrity check parameters that ... | 10/28/2008 |
| 7437658 | Disk array device, parity data generating circuit for RAID and Galois field multiplying circuit In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects n... | 10/14/2008 |
| 7434149 | Prediction device and method applied in a Viterbi decoder A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. Th... | 10/07/2008 |
| 7433793 | Error detection apparatus and method and signal extractor A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through th... | 10/07/2008 |
| 7434128 | Systems and methods for identifying system links In one embodiment, a method for identifying links in a system under evaluation includes assigning unique identifiers to drivers of the system, emitting the identifiers from the drivers on associated links, collecting data received by receivers of the system, and com... | 10/07/2008 |
| 7434151 | Read control systems and methods A read control system and method for a memory device are provided. One embodiment of a system, among others, includes dump logic coupled to a data source, said dump logic configured to receive a first group of a defined slice of data and a second group of the define... | 10/07/2008 |
| 7434152 | Multiple-level data compression read mode for memory testing Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeatin... | 10/07/2008 |
| 7421565 | Method and apparatus for indirectly addressed vector load-add -store across multi-processors A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 09/02/2008 |
| 7395496 | Systems and methods for enhanced stored data verification utilizing pageable pool memory The present invention utilizes pageable pool memory to provide, via a data verifier component, data verification information for storage mediums. By allowing the utilization of pageable pool memory, overflow from the pageable pool memory is paged and stored in a vir... | 07/01/2008 |
| 7391723 | Frame-level fibre channel CRC on switching platform A method and apparatus is presented for performing a sequence-level CRC calculation on fiber channel communications within a switching platform domain. A CRC generator searches the data communication for frames that contain the type of data for which a sequence-leve... | 06/24/2008 |
| 7389390 | Method, microprocessor system for critical safety regulations and the use of the same In a method of operating a microprocessor system provided with safety functions, which comprises two or more processor cores (1, 2) and periphery elements (5, 7) on a common chip carrier, to which the cores can have access for write or read operations,... | 06/17/2008 |
| 7385929 | Method and system for detecting false packets in wireless communications systems Specific bits of an incoming transmission are compared against a predetermined bit pattern. If the selected bits do not match the predetermined bit pattern, then the incoming transmission is rejected as a false packet. The predetermined bit pattern can include legal... | 06/10/2008 |
| 7376889 | Memory device capable of detecting its failure A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data inp... | 05/20/2008 |
| 7373572 | System pulse latch and shadow pulse latch coupled to output joining circuit In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data ... | 05/13/2008 |
| 7370230 | Methods and structure for error correction in a processor pipeline Methods and structures for an improved processor pipeline to eliminate the effect of correctable soft errors on processor/memory pipeline performance. Features and aspects hereof provide that the pipeline is extended by the addition of one or more information correc... | 05/06/2008 |
