Class 714/763 - Memory access

Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter in which digital data being written into
No. of patents: 896
Last issue date: 02/14/2012

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Number	Title	Issue Date
8117518	Signal processing apparatus and a data recording and reproducing apparatus including local memory processor In a data recovery processing, the conventional overhead, primarily, latency due to a rotational recording media is removed. Secondary, in a signal processing or in a recording and reproducing apparatus, reliability of data reproduction is improved by repeatedly pro...	02/14/2012
8112692	Flash memory device error correction code controllers and related methods and memory systems An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error corre...	02/07/2012
8103937	Cas command network replication In an embodiment, a method and computer product is presented for executing a command in a replicated environment comprising a replication appliance and a production site, the method comprising: intercepting the command at a splitter; wherein the command comprises a ...	01/24/2012
8103936	System and method for data read of a synchronous serial interface NAND A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory ...	01/24/2012
8099650	L2 ECC implementation One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bi...	01/17/2012
8095851	Storage subsystem capable of adjusting ECC settings based on monitored conditions A storage subsystem monitors one or more conditions related to the probability of a data error occurring. Based on the monitored condition or conditions, the storage subsystem adjusts an error correction setting, and thus the quantity of ECC data used to protect dat...	01/10/2012
8095852	Data recorder A data recorder includes a first memory element including read/write capability, a second memory element including non-volatile memory and a controller for realizing memory management functions. The controller responds to a predetermined triggering event by writing ...	01/10/2012
8086937	Method for erasure coding data across a plurality of data stores in a network An efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. A data store is a persistent memory for storing a data block. Such data stores include, without limitation, a group of disks, a group of ...	12/27/2011
8086936	Performing error correction at a memory device level that is transparent to a memory channel A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device....	12/27/2011
8082482	System for performing error correction operations in a memory hub device of a memory module A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a...	12/20/2011
8078938	Semiconductor memory, semiconductor memory system, and error correction method for semiconductor memory Aspects of the embodiment include providing a semiconductor memory comprising; a plurality of memory blocks that includes a plurality of regular memory cells; a plurality of first parity blocks that are disposed in accordance with the plurality of memory blocks, whe...	12/13/2011
8078937	Memory-module controller, memory controller and corresponding memory arrangement, and also method for error correction A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of...	12/13/2011
8078939	Interleaving redundancy apparatus and method One embodiment of the invention relates to a network communication device. The network communication device includes a network interface configured to receive an initial data stream. The network communication device also includes an interleaving redundancy encoder t...	12/13/2011
8074148	Memory management method and controller for non-volatile memory storage device A memory management method and a controller for a non-volatile memory storage device are provided. The memory management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by ...	12/06/2011
8069396	Storage device for refreshing data pages of flash memory based on error correction code and method for the same A storage device for refreshing pages of a flash memory comprises a flash memory, an ECC detector and a controller. The flash memory has a plurality of pages, and each page comprises a data area for storing data and a spare area for storing error correction code (EC...	11/29/2011
8065588	Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo...	11/22/2011
8065589	Semiconductor memory device A semiconductor memory device includes a memory cell array from which all bits of a data signal having a first number of the bits composed of a main data signal and an error detection/correction code data signal are simultaneously read, a sense amplifier for amplify...	11/22/2011
8065590	Disk controller methods and apparatus with improved striping, redundancy operations and interfaces A RAID disk drive controller (FIG. 33) implements disk storage operations, including striping and redundancy operations with multiple disk drives connected via respective SATA ports (520). Configurable data path switch logic (460) provides dynam...	11/22/2011
8060806	Estimation of non-linear distortion in memory devices A method for operating a memory (24) includes storing data in analog memory cells (32) of the memory by writing respective analog values to the analog memory cells. A set of the analog memory cells is identified, including an interfered cell having a d...	11/15/2011
8046664	Information processing apparatus and program for controlling the same An information processing apparatus is configured to be backed up by a battery so that information in a main memory of the apparatus can be retained when a power supply for the apparatus is stopped. The apparatus stores kernel information in a kernel information tab...	10/25/2011
8042020	Data error correction circuit, integrated circuit for data error correction, and method of performing data error correction A data error correction circuit includes a plurality of one-bit registers, a data error detection unit and a data error correction unit. The data error detection unit detects whether all the data values stored in the plurality of the registers are equal. The data co...	10/18/2011
8042021	Memory card and memory controller A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an...	10/18/2011
8032814	Writing and reading of data in probe-based data storage devices Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method p...	10/04/2011
8028218	Writing and reading of data in probe-based data storage devices Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method p...	09/27/2011
8024642	System and method for providing constrained transmission and storage in a random access memory A system and method for providing constrained transmission and storage in a random access memory. A system includes a memory device for providing constrained transmission and storage. The memory device includes an interface to a data bus, the data bus having a previ...	09/20/2011
8015470	Apparatus and method for decoding bursts of coded information A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory...	09/06/2011
8010873	Systems and methods for efficient uncorrectable error detection in flash memory A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data ...	08/30/2011
8010872	Electronic controller The invention improves safety of an electronic controller using a nonvolatile memory MRAM able to easily perform reading and writing operations at high speed. Therefore, MRAM for writing a control program from an external tool has a correction code adding writing ci...	08/30/2011
8006164	Memory cell supply voltage control based on error detection For one embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memo...	08/23/2011
8006165	Memory controller and semiconductor memory device A memory controller includes a buffer to which data, which is to be transferred to a memory, is input, an ECC parity generating unit which generates an ECC parity in units of a predetermined data length from the data which is to be transferred to the memory, and a m...	08/23/2011
8001441	Nonvolatile memory with modulated error correction coding Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of th...	08/16/2011
8001443	Data storage apparatus, data storage controller, and related automated testing method A data storage controller for controlling each data access of a data storage element is disclosed. The data storage controller includes a processing unit and a storage unit. The processing unit is utilized for executing an automated testing program on the data stora...	08/16/2011
8001442	Data-processing system for measurement devices The present invention provides a data-processing system for measurement devices, which performs a step-by-step sequence of data-processing tasks. In a conventional data-processing system, a failure in one data-processing task also causes the subsequent tasks to be u...	08/16/2011
7992071	Method for implementing error-correction codes in non-volatile memory A method in a data storage device for storing a plurality of data bits into a non-volatile memory includes transforming a plurality of data bits to be stored in a non-volatile memory device to generate a plurality of transformed data bits. The method further include...	08/02/2011
7984357	Implementing minimized latency and maximized reliability when data traverses multiple buses A memory controller and methods implement minimized latency and maximized reliability when data traverses multiple buses. The memory controller includes a dynamic random access memory (DRAM) error correcting code (ECC) checking and correcting circuit and a high spee...	07/19/2011
7984358	Error-correction memory architecture for testing production errors A system includes a first circuit generating error-correction (EC) bits based on test data. Memory comprises a plurality of memory lines each including a data portion storing the test data and an error-correction (EC) portion storing corresponding ones of the EC bit...	07/19/2011
7975205	Error correction algorithm selection based upon memory organization A method is provided for implementing at least one of a number of error correction algorithms operable on a memory. In the method, each of the error correction algorithms is provided. At least one of the error correction algorithms is then selected based on the orga...	07/05/2011
7975206	Information recording device and method, information reproducing device and method, recording medium, program, and disc recording medium An ECC block is constituted by RS(248,216,33). Of a data length of 216 bytes (symbols), only 16 bytes are allocated to BCA data and the remaining 200 bytes are used for fixed data having a predetermined value. Using the fixed data of 200 bytes and the BCA data of 16...	07/05/2011
7971123	Multi-bit error correction scheme in multi-level memory storage system A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compar...	06/28/2011
7962832	Method for detecting memory error A method for easily detecting a memory error that may occur when a memory is accessed or an allocated memory is freed in the process of developing software is disclosed. The memory error detecting method includes: (a) generating an original block indication variable...	06/14/2011

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Class 714/763 - Memory access