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Class 714/760 - Threshold decoding (e.g., majority logic)


Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter the decoder operates upon a corrupted received
No. of patents: 63
Last issue date: 02/21/2012


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NumberTitleIssue Date
8122318Decoding apparatus and method for a perfect difference-set cyclic code and a difference-set cyclic code
A decoding apparatus includes a decoder register for receiving data having a codeword including null data bits, and decoding the received data while shifting Bit Under Decoding (BUD) by one bit. A connection unit outputs a check result by applying a predetermined ch...
02/21/2012
8086935Soft error correction for a data storage mechanism
An apparatus and method are disclosed for correcting errors in data obtained from read operations on a storage medium. Errors that occur in a minority of read operations for the data are corrected by a voting technique. The data may then be processed with error corr...
12/27/2011
7904788Methods of varying read threshold voltage in nonvolatile memory
Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. ...
03/08/2011
7849380Interleaver mode detection in a digital video receiver
A method and apparatus for decoding received digital data representing video, audio, information or a combination thereof. After a forward error correction (FEC) frame sync lock is detected, a counter is incremented corresponding to the number of identical control w...
12/07/2010
7730381Erasure detection and power control for a transport channel with unknown format in a wireless communication system
Erasure detection and power control are performed for an intermittently active transport channel with unknown format. A receiver processes each received block and determines whether it passes or fails CRC. For each received block with CRC failure, the receiver perfo...
06/01/2010
7634706Majority-detected erasure enhanced error correction
A system for enhancing the error correction capability of an error correction code (“ECC”) during error recovery operations accumulates, for respective bits, counts of the number of times the bits are detected as 1s in multiple re-reads of a data signal. The sys...
12/15/2009
7613981System and method for reducing power consumption in a low-density parity-check (LDPC) decoder
A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered...
11/03/2009
7539922Bit failure detection circuits for testing integrated circuit memories
A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality of bytes of data read from the memory device against a plurality of b...
05/26/2009
7536626Power control using erasure techniques
Techniques for performing erasure detection and power control for a transmission without error detection coding are described. For erasure detection, a transmitter transmits codewords via a wireless channel. A receiver computes a metric for each received codeword, c...
05/19/2009
7530004Error correction apparatus using forward and reverse threshold functions
An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the threshold logic units decodes the data stream based on an advancing time st...
05/05/2009
7461326Information processing method capable of detecting redundant circuits and displaying redundant circuits in the circuit design process
The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing circuit operation information that uses hardware description language and ...
12/02/2008
7428688Method of detecting two-dimensional codes
A method of detecting two-dimensional codes using a plurality of light and dark data bits arranged two-dimensionally. The method includes detecting the code as a gray scale value image, splitting the detected gray scale value image into image areas corresponding to ...
09/23/2008
7406653Anomaly detection based on directional data
Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object. An anomaly detecting method includes: sequentially generating directional data indicating a feature of each piece of monitored data correspondingly to...
07/29/2008
7373581Device, program, and method for decoding LDPC codes
A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing...
05/13/2008
7363553System and method for adjusting soft decision thresholds in a soft-decision error correction system
The soft decision thresholds in a soft decision forward error correction (FEC) system may be adjusted based on mutual information of a detected signal. In one embodiment, a recursive algorithm may be used to optimize threshold values by maximizing the mutual informa...
04/22/2008
7353170Noise-adaptive decoding
In one aspect the invention is a method for decoding. The method includes receiving encoded data and decoding the encoded data using a noise-adaptive decoder. The data may include first-order Reed-Mueller (FORM) based codes. The data may be based on Complementary Co...
04/01/2008
7320095Optimization of the decision threshold for binary signals
A threshold value is set in a decision circuit receiving a transmitted stream of binary symbols from a network link. The decision circuit uses the threshold value for detecting whether a 1 or a 0 is received to produce an output stream having a low bit error rate. B...
01/15/2008
7318186Decoding method, decoding apparatus, and program to decode low density parity check codes
The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to ...
01/08/2008
7313748FEC decoder and method
A method is described for FEC decoding a signal which has become affected by transmission errors, the original signal being transmitted together with parity data. The method comprises: receiving (5) the original signal (DATA) and parity data (ECC DATA) with e...
12/25/2007
7292655Apparatus and method and decoding biphase signals
A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinat...
11/06/2007
7272771Noise and quality detector for use with turbo coded signals
In one aspect this invention provides a method to operate a decoder, and a decoder that operates in accordance with the method. The method includes monitoring, during operation of the decoder on a signal received from a channel, the value of at least one extrinsic v...
09/18/2007
7257760Early decoding of a control channel in a wireless communication system
Techniques are provided for performing early decoding of a message on a control channel in a wireless (e.g., GSM) communication system. In a GSM system, a message for a paging channel is transmitted in four bursts. For early decoding in GSM, a terminal initially rec...
08/14/2007
7246303Error detection and recovery of data in striped channels
In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized ...
07/17/2007
7236005Majority voter circuit design
A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pair...
06/26/2007
7162241Method for managing multicast group in mobile communication system
A multicast service of a 3GPP Universal Mobile Telecommunications System (UMTS) is disclosed. By allowing an RNC to manage multicast group member information by multicast services on multicast areas, when a user terminal being currently provided with an MBMS service...
01/09/2007
7146553Error correction improvement for concatenated codes
An enhanced forward error correction system is disclosed. Transmitted data is encoded into codewords in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes in each dimension, with corrected data provided as an output from ...
12/05/2006
7134066Generalized parity stripe data storage array
The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplie...
11/07/2006
7130934Methods and apparatus for providing data transfer control
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work ind...
10/31/2006
7103825Decoding error-correcting codes based on finite geometries
A method decodes a received word for a binary linear block code based on a finite geometry. First, a parity check matrix representation of the code is defined. The received word is stored in a channel register. An active register represents a current state of the de...
09/05/2006
7095807Method for decoding biphase signals
A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d1) is derived. From this, associated bit combinations (St1,...
08/22/2006
7069494Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a pl...
06/27/2006
7051268Method and apparatus for reducing power consumption of a decoder in a communication system
A method and an apparatus for reducing power consumption of a decoder in a communication system are disclosed. In a communication system communicating a packet, the packet can be arranged among slots of a communication channel so that each slot following the first s...
05/23/2006
6982659Method and apparatus for iterative decoding
Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature...
01/03/2006
6941506Switching circuit for decoder
A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome of the received code signal, when the occurrence of an even (and non-z...
09/06/2005
6910173Word voter for redundant systems
The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n modules. A voter decision is generated by the word voter utilizing a wor...
06/21/2005
6686853Method and apparatus for iterative decoding
Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previou...
02/03/2004
6633615Trellis transition-probability calculation with threshold normalization
A circuit performs threshold normalization of accumulated transition probabilities for a given state of a state transition trellis in a maximum likelihood detector. Threshold normalization may be accomplished by comparison and setting of a single bit in s...
10/14/2003
6167552Apparatus for convolutional self-doubly orthogonal encoding and decoding
An encoder and decoder for generating and decoding convolutional codes of improved orthogonality. In an exemplary embodiment the encoder includes a K-bit length shift register for receiving an input serial stream of information bits and providing for each...
12/26/2000
6122767Method and apparatus for noise reduction of cyclic signal by selecting majority logic state of corresponding portions of plural cycles
An EDTV application utilizing a Synchronous Vector Processor (SVP) includes the operation whereby noise is reduced in the operation to demodulate the chroma signal. Initially, the NTSC composite video is separated into the luminance (Y) and the chroma (C)...
09/19/2000
6119937Information reproduction system, information recording system and information recording medium utilizing an optically readable DOT code
A threshold determination/binarization circuit and a recording medium for an information reproduction system, wherein the diameter of a reference dot detected by a reference dot diameter detection section is compared with a predetermined dot diameter as a...
09/19/2000
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