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| Number | Title | Issue Date |
| 8190966 | Systems and methods for implementing end-to-end checksum A network device includes input logic and output logic. The input logic receives multiple packets, where each of the multiple packets has a variable length, and generates a first error detection code for one of the received multiple packets. The input logic further ... | 05/29/2012 |
| 8190967 | Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method The present invention relates to a low density parity check (LDPC) encoding method and an apparatus thereof. In the LDPC encoding method, a matrix multiplication corresponding to ET−1 and T−1 is eliminated according to a structural characte... | 05/29/2012 |
| 8190968 | Semiconductor memory device and data error detection and correction method of the same A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermine... | 05/29/2012 |
| 8185799 | Transmitting/receiving system and method of processing broadcast signal in transmitting/receiving system A receiving system and a method of processing data are disclosed herein. The receiving system includes a receiving unit, an equalizer, a block decoder, and an RS frame decoder. The receiving unit receives and demodulates a broadcast signal. Herein, the broadcast sig... | 05/22/2012 |
| 8185798 | Techniques for reducing joint detection complexity in a channel-coded multiple-input multiple-output communication system A technique for joint detection of channel-coded signals in a multiple-input multiple-output system includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel-coded signals in the first symbol stream and... | 05/22/2012 |
| 8185797 | Basic matrix, coder/encoder and generation method of the low density parity check codes The invention relates to a base matrix, a encoder/decoder of Low Density Parity Check (LDPC) codes and a generation method thereof. The encoder/decoder is determined uniquely by the parity check matrix of the LDPC codes. With different code sizes, said parity check ... | 05/22/2012 |
| 8181084 | Detecting insertion/deletion using LDPC code Systems and methods are provided that use LDPC codes to determine the locations of insertions or deletions within bit-strings of information transmitted through communication channels and which notify a LDPC decoder of the locations of the insertions or deletions pr... | 05/15/2012 |
| 8181085 | Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity ch... | 05/15/2012 |
| 8181083 | Methods and architectures for layered decoding of LDPC codes with minimum latency An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for ... | 05/15/2012 |
| 8176383 | Method of constructing low density parity check code, method of decoding the same and transmission system for the same The present invention relates to a method of constructing a low density Parity Check code, a method of decoding the same and a transmission system using the same. The method comprises steps of: constructing a low density Parity Check matrix of the low density Parity... | 05/08/2012 |
| 8176384 | Method and apparatus for channel encoding and decoding in a communication system using low-density-parity-check codes A method and apparatus for encoding and decoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The encoding method includes determining a modulation scheme for transmitting a symbol; determining a shortening pattern in considerati... | 05/08/2012 |
| 8176385 | Apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs) The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to... | 05/08/2012 |
| 8176382 | Storage apparatus, method for accessing data and for managing memory block A method for managing a memory block is provided. In this method, a plurality of block tables having different storing priorities is provided. In addition, the number of error correction bits in the memory block is checked. Thereby, in the present invention, data ca... | 05/08/2012 |
| 8171374 | LDPC check matrix generation method, check matrix generator, and code retransmission method A check matrix generation method for generating a check matrix H1 of a code H1 from a check matrix H0 of a code C0, where codes C0 and C1 are LDPC systematic codes having different encoding ratios in a rate-compatible relati... | 05/01/2012 |
| 8171371 | Inspection matrix generation method, encoding method, communication device, communication system, and encoder A regular qc matrix is generated in which cyclic permutation matrices with specific regularity are arranged in row and column directions. A mask matrix supporting multiple encoding rates is generated for making the regular qc matrix into irregular. A specific cyclic... | 05/01/2012 |
| 8171372 | Feedback signaling error detection and checking in MIMO wireless communication systems A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit. ... | 05/01/2012 |
| 8171373 | Coding circuit for recording data on DVD disk A coding circuit that includes a buffer manager and a coding block is provided for generating product codes for parity checks as error correction code and adding the product codes to digital data to be recorded in a record medium. ... | 05/01/2012 |
| 8171375 | Distributed processing LDPC (low density parity check) decoder Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requiremen... | 05/01/2012 |
| 8171370 | Method and apparatus for applying forward error correction in 66b systems A method and apparatus for applying Forward Error Correction (FEC) in 66b systems. For a user data, the apparatus uses a method comprising the steps of generating one or more data blocks using a 66b code format and the user data; generating one or more FEC parity bl... | 05/01/2012 |
| 8166367 | Method and apparatus for encoding and decoding channel in a communication system using low-density parity-check codes A method for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The method includes generating a plurality of column groups by grouping (categorizing) columns corresponding to an information word in a parity-check matrix of th... | 04/24/2012 |
| 8166366 | Partial configuration of programmable circuitry with validation Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation,... | 04/24/2012 |
| 8161351 | Systems and methods for efficient data storage Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a sec... | 04/17/2012 |
| 8161350 | Method and system for encoding a data sequence A communication method and a communication system including a first entity (3) including an information source (9) and a coder device (11) connected by a channel (7) transmitting data to a second entity (5) including a decoder devi... | 04/17/2012 |
| 8156401 | Validating data using processor instructions In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic r... | 04/10/2012 |
| 8156400 | Embedded parity coding for data storage A decoder memory system comprises a first memory comprising at least a portion of a parity check matrix H. A second memory receives the portion from the first memory and that is associated with a previous decoding iteration. A third memory communicates with the firs... | 04/10/2012 |
| 8151163 | Automatic defect management in memory devices A method for storing data in a memory (28) that includes analog memory cells (32) includes identifying one or more defective memory cells in a group of the analog memory cells. An Error Correction Code (ECC) is selected responsively to a characteristic... | 04/03/2012 |
| 8151164 | Method and apparatus for encoding and decoding high speed shared control channel A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minim... | 04/03/2012 |
| 8145975 | Universal packet loss recovery system for delivery of real-time streaming multimedia content over packet-switched networks The Universal Packet Loss Recovery System is capable of recovering end-to-end network packet losses to obtain reliable end-to-end network delivery of multimedia streaming content over Internet Protocol (IP) networks, where packet losses appear above the transport la... | 03/27/2012 |
| 8145976 | Error correcting In one or more embodiments, a method, computer-readable media, and/or computational unit acts or is capable of receiving, from a single, integrated memory, current and previous iterations of Log Likelihood Ratio (“LLR”) parameters for a current iteration of a Lo... | 03/27/2012 |
| 8140936 | System for a combined error correction code and cyclic redundancy check code for a memory channel A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway betwee... | 03/20/2012 |
| 8136010 | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple o... | 03/13/2012 |
| 8136011 | Broadcast receiver and method of processing data A broadcast receiver and a method of processing data are disclosed. The broadcast receiver includes a signal receiving unit, a RS frame decoder, a decoding unit, a text-to-speech (TTS) module, a voice output unit, and a control unit. The signal receiving unit receiv... | 03/13/2012 |
| 8132074 | Reliability, availability, and serviceability solutions for memory technology Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initia... | 03/06/2012 |
| 8122317 | Two-dimensional parity technique to facilitate error detection and correction in memory arrays The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays, each of which has various rows and columns of cells. A row of bits in a super bundle is referred to as a row bundle. A super bundle includes n... | 02/21/2012 |
| 8122315 | LDPC decoding apparatus and method using type-classified index Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory includ... | 02/21/2012 |
| 8122316 | Error detector and error detection method An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector c... | 02/21/2012 |
| 8112691 | Method for efficient generation of a Fletcher checksum using a single SIMD pipeline The generation of Fletcher/Alder partial checksums are transformed from a space that requires integer multiplications and additions to a space that requires only integer additions and shifts on a single SIMD pipeline capable processor. This transformation permits th... | 02/07/2012 |
| 8112690 | Method, system, and computer program product for connection state recovery after fault A method, system, and computer program product for connection state recovery of a connection after fault in a networked channel-to-channel computer system are provided. The method includes identifying essential data in response to detecting a state change in a chann... | 02/07/2012 |
| 8108753 | Method of computing partial CRCs Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated ... | 01/31/2012 |
| 8108754 | Programmable logic device programming verification systems and methods In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The metho... | 01/31/2012 |
