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| Number | Title | Issue Date |
| 8161348 | Systems and methods for low cost LDPC decoding Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit,... | 04/17/2012 |
| 8161349 | Data parallelizing receiver Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the para... | 04/17/2012 |
| 8136009 | Circuit arrangement and method for error detection and arrangement for monitoring of a digital circuit A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E1, . . . , En for inputting n (n≧2) information bits x1, . . . , xn and m binary outputs for outputting m (m≧1) check bits c1, . . . , cm. The combinati... | 03/13/2012 |
| 8069389 | Error correction circuit and method, and semiconductor memory device including the circuit An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficie... | 11/29/2011 |
| 8051359 | System and method for optimizing iterative circuit for cyclic redundency check (CRC) calculation A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to e... | 11/01/2011 |
| 8046661 | Symbol error correction by error detection and logic based symbol reconstruction Methods and apparatus for creating codewords of n-valued symbols with one or more n-valued check symbols are disclosed. Associating the codewords with a matrix allows for detection of one or more symbols in error and the location of such symbols in error. Methods to... | 10/25/2011 |
| 8032813 | Concurrent production of CRC syndromes for different data blocks in an input data sequence Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of pa... | 10/04/2011 |
| 7895499 | Method and apparatus for checking pipelined parallel cyclic redundancy A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input ... | 02/22/2011 |
| 7627801 | Methods and apparatus for encoding LDPC codes Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identic... | 12/01/2009 |
| RE40991 | Fast cyclic redundancy check (CRC) generation A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a da... | 11/17/2009 |
| 7590916 | Cyclic redundancy checking value calculator A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cy... | 09/15/2009 |
| RE40684 | Fast cyclic redundancy check (CRC) generation A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is iteratively performed, one iteration at a time. Further, the selection of... | 03/24/2009 |
| 7395483 | Method and apparatus for performing error-detection and error-correction One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line... | 07/01/2008 |
| 7383464 | Non-inline transaction error correction Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of oper... | 06/03/2008 |
| 7373525 | Data processing method and data checking method Cyclic-redundancy-check (CRC) processing is executed on data blocks each having a predetermined data amount, thereby calculating respective CRC values for the data blocks. Furthermore, CRC processing is executed on the respective CRC values a number of times determi... | 05/13/2008 |
| 7363574 | Method and system for parallel CRC calculation A system and method for a parallel CRC calculation is provided. A set of parallel inputs are loaded into a control register, and this control register is then used with a parallel table look-up operation to look up CRC entries for each of the inputs using a single i... | 04/22/2008 |
| 7363573 | Method and apparatus for a dedicated cyclic redundancy check block within a device A dedicated Cyclic Redundancy Check (CRC) block within an Integrated circuit IC), for example, a Programmable Logic Device (PLD), allows direct access to the CRC block from within the programmable logic of the IC. Accessibility to the CRC block is achieved from any ... | 04/22/2008 |
| 7360015 | Preventing storage of streaming accesses in a cache In one embodiment of the present invention, a method may include determining whether requested information is part of a streaming access, and directly writing the requested information from a storage device to a memory if the requested information is part of the str... | 04/15/2008 |
| 7360196 | Technology mapping for programming and design of a programmable logic device by equating logic expressions A programmable logic device (“PLD”) architecture and a user logic design are modeled logically to find an efficient programming solution for the user logic design on the PLD architecture. The logical models are converted to equations—e.g., by representing them... | 04/15/2008 |
| 7360142 | Methods, architectures, circuits, software and systems for CRC determination Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (i) partitioning the unit of digital data into one or more full data lines and a remainder, wherein each of the full data lines comprise... | 04/15/2008 |
| 7343472 | Processor having a finite field arithmetic unit utilizing an array of multipliers and adders A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily stores an instruction that includes at least one of: an operational c... | 03/11/2008 |
| 7342938 | Spectrally efficient approach to protection of key elements in a non-homogenous data stream A system and method for transmitting a file stream using quality of service capable links. The system has a network capable of supporting quality of service negotiations and an embedded component capable of negotiating different quality of service levels for a plura... | 03/11/2008 |
| 7330489 | Distributed data synchronization apparatus and method Disclosed is a method and apparatus for synchronizing data in a number of separate integrated circuits. In one embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integr... | 02/12/2008 |
| 7328396 | Cyclic redundancy check generating circuit A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partiti... | 02/05/2008 |
| 7320101 | Fast parallel calculation of cyclic redundancy checks Circuits, methods, and apparatus for the fast parallel calculation of CRCs. One embodiment provides a feedforward path that combines common terms to simplify input logic. Common expressions that appear in multiple terms in the feedforward path are implemented using ... | 01/15/2008 |
| 7318189 | Parallel convolutional encoder Methods and devices for encoding in parallel a set of data. bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encod... | 01/08/2008 |
| 7310757 | Error detection on programmable logic resources Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compare... | 12/18/2007 |
| 7299399 | Method and apparatus for parallelly processing data and error correction code in memory A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcti... | 11/20/2007 |
| 7299398 | Data generating method for forming desired CRC code A method of generating a CRC code to determine a variable field value for equalizing a CRC value, which is calculated based on data including the variable field value of a variable field included in a data field according to a generator polynomial, to a desired CRC ... | 11/20/2007 |
| 7295554 | Word Multiplexing of encoded signals into a higher bit rate serial data stream A method of data communication that includes receiving a plurality of 8b/10b encoded data streams. The method also includes multiplexing, on a word by word basis, each of the plurality of data streams and forming a new encoded data stream. The method also includes g... | 11/13/2007 |
| 7281192 | LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment... | 10/09/2007 |
| 7278090 | Correction parameter determination system An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register posi... | 10/02/2007 |
| 7269785 | Digital manipulation of video in digital video player According to the invention, a technique for operating a digital versatile disk (DVD) system is disclosed. First digital information is read from a DVD player. The first digital information is decompressed to create second digital information that is stored. In order... | 09/11/2007 |
| 7266760 | Method and apparatus for calculating cyclic redundancy checks for variable length packets Cyclic redundancy checking operations may be performed on a message made up of full words and a partial word. An accumulator value for the cyclic redundancy checking operations may be updated as the full words and partial word are processed. The partial word may be ... | 09/04/2007 |
| 7260540 | Encoding device, decoding device, and system thereof utilizing band expansion information A decoding device (30a) comprises a narrow-band decoding unit (31) operable to reproduce a PCM signal (P1) from a narrow-band bit stream included in a wide-band bit stream (S0), a wide-band decoding unit (32) operable to rep... | 08/21/2007 |
| 7260765 | Methods and apparatus for dynamically reconfigurable parallel data error checking In a first aspect, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the ... | 08/21/2007 |
| 7254769 | Encoding/decoding apparatus using low density parity check code Disclosed is an encoding/decoding apparatus of a HARQ system using LDPC codes. A first LDPC code encoding apparatus encodes input information data and transmits the encoded data to the decoding apparatus. An interleaver interleaves the input information data. A seco... | 08/07/2007 |
| 7249306 | System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage de... | 07/24/2007 |
| 7246294 | Method for iterative hard-decision forward error correction decoding A method for hard-decision forward error correction decoding is described. A method comprises iteratively decoding a set of hard input data that has been transmitted optically, the set of hard input data having a set of information symbols, each of the set of inform... | 07/17/2007 |
| 7246289 | Memory integrity self checking in VT/TU cross-connect A method and apparatus for detecting errors in a memory includes generating a first check word based on incoming data and generating a second check word based on stored data. The method includes comparing the first check word to the second check word, generating a c... | 07/17/2007 |
