Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 8161346 | Data refresh apparatus and data refresh method According to one embodiment, a data refresh apparatus which refreshes data stored in a storage device having storage areas, comprises an error detector configured to detect a number of errors of data stored in a storage area of the storage device, an error correctio... | 04/17/2012 |
| 8108750 | RAID 3+3 A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before da... | 01/31/2012 |
| 8032810 | Non-volatile semiconductor storage device and non-volatile storage system This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural th... | 10/04/2011 |
| 7870460 | Magnetic disk drive capable of refreshing data written to disk and data refresh method According to one embodiment, the controller controls a data refresh operation. The data refresh operation comprises a refresh-data read operation of reading L blocks of data by a head from a track to be refreshed on a disk, a data backup-write operation of writing t... | 01/11/2011 |
| 7836374 | Memory controller method and system compensating for memory cell data losses A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal r... | 11/16/2010 |
| 7712007 | Semiconductor memory device having data holding mode using ECC function When memory cells enter an operation mode which performs only data holding, a control circuit controls the memory cells and an ECC circuit as follows. A plurality of data are read out to generate and store a check bit for error detection and correction. Refreshing i... | 05/04/2010 |
| 7647543 | Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with... | 01/12/2010 |
| 7565593 | Apparatus and method for memory bit-swapping-within-address-range circuit A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows bein... | 07/21/2009 |
| 7526709 | Error detection and correction in a CAM An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of th... | 04/28/2009 |
| 7464315 | Semiconductor memory device Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried... | 12/09/2008 |
| 7461320 | Memory system and method having selective ECC during low power refresh A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching th... | 12/02/2008 |
| 7447974 | Memory controller method and system compensating for memory cell data losses A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal r... | 11/04/2008 |
| 7447973 | Memory controller method and system compensating for memory cell data losses A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal r... | 11/04/2008 |
| 7428687 | Memory controller method and system compensating for memory cell data losses A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal r... | 09/23/2008 |
| 7428685 | Cyclic error compensation in interferometry systems The invention features a method including: (i) providing an interference signal S(t) from two beams directed along different paths, wherein the signal S(t) is indicative of changes in an optical path difference n{tilde over (L)}(t) between the different paths, where... | 09/23/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7334177 | Method and system for tracking sequence numbers The invention concerns a method (500) for tracking sequence numbers. The method includes the steps of detecting (512) an error in a first set of data (120), determining (514) a range (144) of possible sequence numbers (122) ... | 02/19/2008 |
| 7331011 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second... | 02/12/2008 |
| 7327218 | Electronic identification system with forward error correction system An electronic radio frequency (RF) identification system 10 is disclosed and claimed. The system includes an interrogator 11 and a plurality of RF transponders 12.1 to 12.n. In use, each transponder is operative in response to an i... | 02/05/2008 |
| 7328365 | System and method for providing error check and correction in memory systems A system for providing error check and correction (ECC) is provided. The system includes an ECC interface for storing ECC codes in a first memory system and storing data in a second memory system. The ECC interface corrects errors in the data received from the secon... | 02/05/2008 |
| 7328304 | Interface for a block addressable mass storage system A host controller interface to manage the complexity of accessing mass storage that takes into account the special handling needs of various memory technologies such as polymer memories. ... | 02/05/2008 |
| 7325155 | Embedded system with reduced susceptibility to single event upset effects An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a ... | 01/29/2008 |
| 7318183 | Data storing method of dynamic RAM and semiconductor memory device When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable... | 01/08/2008 |
| 7313046 | Semiconductor memory devices in which the number of memory banks to be refreshed may be changed and methods of operating the same A semiconductor memory device includes a plurality of memory banks. A refresh control block is responsive to a control address that identifies at least one of the plurality of memory banks to be refreshed. The refresh control block is configured to control refreshin... | 12/25/2007 |
| 7275200 | Transparent error correcting memory that supports partial-word write A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are e... | 09/25/2007 |
| 7275202 | Method, system and program product for autonomous error recovery for memory devices An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addr... | 09/25/2007 |
| 7266759 | Semiconductor integrated circuit device and error checking and correcting method thereof A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time durin... | 09/04/2007 |
| 7251773 | Beacon to visually locate memory module One embodiment disclosed relates to a method of visually locating a memory module. An electronic communication is received by circuitry on the memory module to be visually located. A beacon state in the memory module is activated due to receipt of the electronic com... | 07/31/2007 |
| 7249289 | Method of deciding error rate and semiconductor integrated circuit device An error rate select circuit activated in an information sustaining mode is provided, wherein a plurality of pieces of data are read from a dynamic memory circuit and inspection bits which are used to detect an error existing in the pieces of data are generated. If ... | 07/24/2007 |
| 7237172 | Error detection and correction in a CAM An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of th... | 06/26/2007 |
| 7237175 | Memory circuit When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into mem... | 06/26/2007 |
| 7224628 | Adaptive algorithm for MRAM manufacturing Magnetic Random Access Memory (MRAM) can be programmed and read as fast as Static Random Access Memory (SRAM) and has the non-volatile characteristics of electrically eraseable programmable read only memory (EEPROM), FLASH EEPROM or one-time-programmable (OTP) EPROM... | 05/29/2007 |
| 7219272 | Semiconductor integrated circuit with memory redundancy circuit A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bu... | 05/15/2007 |
| 7184352 | Memory system and method using ECC to achieve low power refresh Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndr... | 02/27/2007 |
| 7171605 | Check bit free error correction for sleep mode data retention A DRAM memory has a reduced refresh rate in a sleep mode to conserve power. Error Correction Codes (ECC) are used to correct errors that may arise due to the reduced refresh rate. ECC encoding occurs at the time of entering the sleep mode and ECC decoding for error ... | 01/30/2007 |
| 7065159 | Compensation based bit-error-rate estimation for convolutionally encoded transmissions in wireless systems In a UMTS (universal mobile telecommunications system) based system, a wireless receiver comprises a convolutional decoder, a processor and memory. The convolutional decoder processes a received signal and provides a Yamamoto-Itoh (YI) metric to the processor. The p... | 06/20/2006 |
| 7051260 | Data storing method of dynamic RAM and semiconductor memory device When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable... | 05/23/2006 |
| 7024599 | System and method for non-causal channel equalization A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing thresholds to distinguish a first bit estimate; comparing the first bit estima... | 04/04/2006 |
| 6958678 | Electronic identification system with forward error correction system An electronic radio frequency (RF) identification system 10 is disclosed and claimed. The system includes an interrogator 11 and a plurality of RF transponders 12.1 to 12.n. In use, each transponder is operative in response to an i... | 10/25/2005 |
| 6941504 | Method and apparatus for test case evaluation using a cyclic redundancy checker The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method provide a CRC function that is used to calculate a CRC value for a portion of memory. The CRC value is compared with an expected CRC valu... | 09/06/2005 |
