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| Number | Title | Issue Date |
| 8185791 | Providing tuning limits for operational parameters in data processing apparatus Tuning limits are set for operational parameters in a processing stage within a data processing apparatus for processing a signal and outputting it at an output time. If a signal output between the output time and a predetermined time later does not have a stable va... | 05/22/2012 |
| 7996743 | Logic circuit testing with reduced overhead An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit ... | 08/09/2011 |
| 7853851 | Method and apparatus for detecting degradation in an integrated circuit chip A system that detects degradation in an integrated circuit chip. During operation, the system monitors a pair of pins on the integrated circuit chip and in doing so, generates a time series of parameters for the pins. The system then determines whether the time seri... | 12/14/2010 |
| 7844876 | Temperature sampling in electronic devices In some embodiments the continuous measuring of temperature in remote memory devices operating within an electrically noisy environment is facilitated by coordinating the progressive approximation of temperature within quiescent periods of non-activity as known by a... | 11/30/2010 |
| 7810006 | Testing system for a device under test A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as to execute a test algorithm, so as to generate a transmission signal... | 10/05/2010 |
| 7774671 | Method and apparatus to adjust voltage for storage location reliability According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storag... | 08/10/2010 |
| 7774670 | Method and apparatus for dynamically determining tester recipes A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested using a test program and the group test parameter. ... | 08/10/2010 |
| 7739573 | Voltage identifier sorting A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then us... | 06/15/2010 |
| 7689887 | Automatic shutdown or throttling of a BIST state machine using thermal feedback A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodi... | 03/30/2010 |
| 7665005 | In situ processor margin testing Embodiments of apparatuses, methods, and systems for in situ processor margin testing are disclosed. In one embodiment, an apparatus includes virtual machine control logic and operating point control logic. The virtual machine control logic is to transfer control of... | 02/16/2010 |
| 7603605 | Performance control of an integrated circuit An integrated circuit is provided with a test circuit element and one or more further circuit elements. The performance of the test circuit element at various settings of a performance controlling parameter is determined. That performance controlling parameter is th... | 10/13/2009 |
| 7587651 | Method and related apparatus for calibrating signal driving parameters between chips A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test ... | 09/08/2009 |
| 7565592 | Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE) The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using sti... | 07/21/2009 |
| 7523373 | Minimum memory operating voltage technique A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that mayb... | 04/21/2009 |
| 7475319 | Threshold voltage control apparatus, test apparatus, and circuit device There is provided a threshold voltage control apparatus that controls a threshold voltage for a level comparing section that detects a logic pattern of an input signal by comparing a level of the input signal with the threshold voltage. The apparatus includes: a plu... | 01/06/2009 |
| 7461317 | System and method for aligning a quadrature encoder and establishing a decoder processing speed A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be us... | 12/02/2008 |
| 7444577 | Memory device testing to support address-differentiated refresh rates A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of stor... | 10/28/2008 |
| 7441173 | Systems, devices, and methods for arc fault detection Certain exemplary embodiments comprise a system that comprises an application specific integrated circuit configured to provide an output signal. The output signal can be configured to trip a device in an electrical circuit responsive to a detected fault. The applic... | 10/21/2008 |
| 7437647 | Mode entry circuit and method An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference voltages by a voltage margin. ... | 10/14/2008 |
| 7437644 | Automatic self-testing of an internal device in a closed system A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system is automatically and periodically performed without triggering from ... | 10/14/2008 |
| 7437620 | Method and system for extending the useful life of another system Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system ... | 10/14/2008 |
| 7437629 | Method for checking the refresh function of an information memory A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these ... | 10/14/2008 |
| 7415646 | PageEXE erase algorithm for flash memory Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of th... | 08/19/2008 |
| 7409617 | System for measuring characteristics of a digital signal An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator... | 08/05/2008 |
| 7395475 | Circuit and method for fuse disposing in a semiconductor memory device A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode i... | 07/01/2008 |
| 7395480 | Test apparatus and test method The present invention provides a test apparatus comprising: a threshold voltage setting unit for setting threshold voltages of a logic device component connected to the signal propagation path; a test signal supply unit for supplying a test signal to the test subjec... | 07/01/2008 |
| 7392444 | Non-volatile memory evaluating method and non-volatile memory The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with respect to hot holes. The present method performs a write operation to... | 06/24/2008 |
| 7383477 | Interface circuit for using a low voltage logic tester to test a high voltage IC The present invention provides an interface circuit for using a low voltage logic tester to test a high voltage IC. The interface circuit is between the high voltage IC and the low voltage logic tester, and is used for converting each output of the high voltage IC t... | 06/03/2008 |
| 7372760 | Semiconductor device and entry into test mode without use of unnecessary terminal A semiconductor device includes a first power supply terminal, a second power supply terminal, a comparison circuit coupled to the first power supply terminal and the second power supply terminal to produce at an output node thereof a signal responsive to a differen... | 05/13/2008 |
| 7373566 | Semiconductor device for accurate measurement of time parameters in operation A memory-logics LSI device forms an input/output path for testing. A memory device has a memory input/output unit,which includes an input/output selector with test function. A test clock signal, which is directly supplied in the test mode, is used to selectively tak... | 05/13/2008 |
| 7370254 | Compressing test responses using a compactor The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover,... | 05/06/2008 |
| 7370247 | Dynamic offset compensation based on false transitions A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detec... | 05/06/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7363568 | System and method for testing differential signal crossover using undersampling System and method for testing differential signal crossover in high-speed electronic equipment. A preferred embodiment comprises a test circuit coupled to a device under test (DUT) and an automatic test equipment (ATE). The test circuit comprises a pair of window co... | 04/22/2008 |
| 7363556 | Testing apparatus and testing method A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail... | 04/22/2008 |
| 7359822 | Testing device A testing device that tests an electronic device includes a test pattern outputting unit operable to output a test pattern to the electronic device, a deciding unit operable to decide whether an output signal from the electronic device satisfies a predetermined cond... | 04/15/2008 |
| 7355458 | Output driver circuit and a method of transmitting an electrical signal via an output driver circuit In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal whic... | 04/08/2008 |
| 7348811 | Equalizing transceiver with reduced parasitic capacitance A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a cor... | 03/25/2008 |
| 7349813 | Fault tolerant power system architecture for fluid flow measurement systems To provide a fault-tolerant architecture to supply electrical operating power in fluid flow measurement applications, apparatus and associated systems, computer program products, and methods include an intelligent power module with redundant and electrically indepen... | 03/25/2008 |
| 7348790 | AC testing of leakage current in integrated circuits using RC time constant Some embodiments of the invention include apparatus and systems having integrated circuits. Terminals or pins of the integrated circuits are configured to be driven to a state, to be floated for a time interval, and to be measured to determine the state of the termi... | 03/25/2008 |
