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| Number | Title | Issue Date |
| 8156396 | Method and system for correcting timing errors in high data rate automated test equipment A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating... | 04/10/2012 |
| 8055969 | Multi-strobe circuit A multi-strobe circuit that latches a signal to be tested, an evaluation target, at each edge timing of a multi-strobe signal having a plurality of edges. An oscillator oscillates at a predetermined frequency in synchronization with a reference strobe signal. A latc... | 11/08/2011 |
| 7941723 | Clock generator and method for providing reliable clock signal using array of MEMS resonators A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated ... | 05/10/2011 |
| 7904776 | Jitter injection circuit, pattern generator, test apparatus, and electronic device Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that are connected in a cascading manner and that each sequentially delay a supplied reference signal by a preset delay amount and a sign... | 03/08/2011 |
| 7900114 | Error detection in an integrated circuit An electronic device includes an integrated circuit operating on the basis of an operating clock signal, an error detection circuit and a control circuit coupled to the error detection circuit. The control circuit is configured to increase the frequency of the opera... | 03/01/2011 |
| 7900113 | Debug circuit and a method of debugging A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each of a subset of the modes of the multi-mode circuit a corresponding debug signal based on a clock signal pr... | 03/01/2011 |
| 7844875 | Programmable test clock generation responsive to clock signal characterization A clock signal within an application-specific integrated circuit (ASIC) is characterized while operating a subsystem. Subsequently, also on the ASIC, a testing clock signal is generated, based on the characterization of the operative clock signal, for purposes of te... | 11/30/2010 |
| 7810005 | Method and system for correcting timing errors in high data rate automated test equipment A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating... | 10/05/2010 |
| 7757145 | Test method, integrated circuit and test system The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generatio... | 07/13/2010 |
| 7757144 | System and method for testing integrated circuit modules comprising a plurality of integrated circuit devices A system and method for testing an integrated circuit module including multiple integrated circuit devices that provide a data strobe signal associated with at least one data signal provided by the same integrated circuit device. A determination of a test outcome fo... | 07/13/2010 |
| 7734976 | Synchronizing control of test instruments A method and apparatus for synchronizing plural test devices coupled to a host. A counter of each of the devices is initialized, and each of the counters is incremented, such as by a periodic signal indicating a start of a data stream. An action, typically either a ... | 06/08/2010 |
| 7681099 | Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test An integrated circuit (1600) includes a debug module (1602) and a clock generator (1610). The debug module (1602) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator (1610 | 03/16/2010 |
| 7669102 | JTAG to SPI PROM conduit A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and r... | 02/23/2010 |
| 7665004 | Timing generator and semiconductor testing apparatus A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outp... | 02/16/2010 |
| 7617431 | Method and apparatus for analyzing delay defect The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integr... | 11/10/2009 |
| 7607061 | Shrink test mode to identify Nth order speed paths In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input cloc... | 10/20/2009 |
| 7587650 | Clock jitter detector A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot ... | 09/08/2009 |
| 7549101 | Clock transferring apparatus, and testing apparatus There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of the reference clock, having a rate clock generating section for genera... | 06/16/2009 |
| 7543210 | Semiconductor device and test system thereof A semiconductor device that includes a clock buffer, which generates an internal clock signal in response to a clock signal and a complementary clock signal if the semiconductor device is operating in a first mode and generates the internal clock signal in response ... | 06/02/2009 |
| 7526704 | Testing system and method allowing adjustment of signal transmit timing A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first ... | 04/28/2009 |
| 7516384 | Semiconductor memory testing device and test method using the same A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided ... | 04/07/2009 |
| 7516385 | Test semiconductor device in full frequency with half frequency tester An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock an... | 04/07/2009 |
| 7512858 | Method and system for per-pin clock synthesis of an electronic device under test A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and distributing said reference clock to a number of electronic circuits, each of... | 03/31/2009 |
| 7487423 | Decoding method, medium, and apparatus A decoding method, medium, and apparatus capable of preventing error propagation and implementing parallel processing. A decoding method includes comparing encoding information with decoding information at synchronization points for detecting a transmission error, a... | 02/03/2009 |
| 7472329 | Shift register, data line driving circuit, scanning line driving circuit, electro-optical device, and electronic apparatus To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit spec... | 12/30/2008 |
| 7461316 | Multi-strobe generation apparatus, test apparatus and adjustment method A multi-strobe generation apparatus for generating a multi-strobe has a plurality of strobes. The multi-strobe generation apparatus includes a shift clock generating section which outputs a shift clock generated by dividing a reference clock at a timing at which eac... | 12/02/2008 |
| 7454681 | Automatic test system with synchronized instruments A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a re... | 11/18/2008 |
| 7444576 | Target value search circuit, taget value search method, and semiconductor test device using the same In a tentative target value calculation section 28, a predetermined value is subtracted from (or added to) a target value Exp to calculate a tentative target value ExpB. In a binary search executing section 25, binary search is executed, and a searchin... | 10/28/2008 |
| 7444560 | Test clocking scheme A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock... | 10/28/2008 |
| 7444570 | Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit g... | 10/28/2008 |
| 7437629 | Method for checking the refresh function of an information memory A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these ... | 10/14/2008 |
| 7434121 | Integrated memory device and method for its testing and manufacture An integrated memory device includes an array of memory cells for storing data, a memory cell selector operationally connected to the array for selecting at least one memory cell of the array, a data interface adapted to store data provided to the data interface in ... | 10/07/2008 |
| 7434114 | Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training se... | 10/07/2008 |
| 7424656 | Clocking methodology for at-speed testing of scan circuits with synchronous clocks A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element i... | 09/09/2008 |
| 7424660 | Synchronization point across different memory BIST controllers A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An ou... | 09/09/2008 |
| 7420400 | Method and apparatus for on-chip duty cycle measurement The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. ... | 09/02/2008 |
| 7412640 | Self-synchronizing pseudorandom bit sequence checker Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In... | 08/12/2008 |
| 7409617 | System for measuring characteristics of a digital signal An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator... | 08/05/2008 |
| 7409621 | On-chip jitter testing On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values. For each delay value, a corresponding output from the circuit under test is compared with a reference sig... | 08/05/2008 |
| 7406646 | Multi-strobe apparatus, testing apparatus, and adjusting method A multi-strobe apparatus for generating multi-strobe having a plurality of strobes is provided, wherein the multi-strobe apparatus includes a clock generating unit which is able to generate a signal for adjustment at a timing at which each of the plurality of strobe... | 07/29/2008 |
