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| Number | Title | Issue Date |
| 8046655 | Area efficient memory architecture with decoder self test and debug capability An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external B... | 10/25/2011 |
| 7836372 | Memory controller with loopback test interface In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operati... | 11/16/2010 |
| 7725795 | Load generating apparatus and load testing method A load generating apparatus for applying a load on a bus of a test target system, has a mode setting register to which an operation mode is set, a data size register to which a data size of one data transfer is set, a register group to which a base address which is ... | 05/25/2010 |
| 7725794 | Instruction address generation for test apparatus and electrical device There is provided a test apparatus that tests a device under test. The test apparatus includes a main memory that stores a test instruction stream determining a test sequence for testing the device under test, a sequence cache memory that caches the test instruction... | 05/25/2010 |
| 7716550 | Semiconductor IC including pad for wafer test and method of testing wafer including semiconductor IC Provided are a semiconductor integrated circuit (IC) including a pad for a wafer test and a method of testing a wafer including a semiconductor IC. The semiconductor IC includes a first address generator, a second address generator, and an address output unit. The f... | 05/11/2010 |
| 7426668 | Performing memory built-in-self-test (MBIST) Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... | 09/16/2008 |
| 7421629 | Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to co... | 09/02/2008 |
| 7415536 | Address query response method, program, and apparatus, and address notification method, program, and apparatus Upon reception of a query about the address of a server from a client, a DNS server sends a query about the address of that server to an external DNS server. The DNS server checks based on the address obtained from the external DNS server if connection to the server... | 08/19/2008 |
| 7415649 | Semi-conductor component test device with shift register, and semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-condu... | 08/19/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7360116 | Built-in self test circuit A built-in self test circuit (BIST circuit) in an LSI includes a verification test pattern generator for generating verification test pattern which is used for verifying the connections in the LSI including the BIST circuit in the design stage thereof, and another t... | 04/15/2008 |
| 7343256 | Configurable voltage regulator A configurable semiconductor has a device characteristic that is controllable as a function of at least one external impedance. A measurement circuit measures an electrical characteristic of the at least one external impedance and determines a select value correspon... | 03/11/2008 |
| 7337378 | Semiconductor integrated circuit and burn-in test method thereof To provide a semiconductor integrated circuit that includes a flash EEPROM on which an efficient burn-in test can be carried out and a burn-in test method thereof. By changing the level of a control signal C1 from the mode selecting unit 40, the operat... | 02/26/2008 |
| 7334171 | Test pattern generating apparatus, circuit designing apparatus, test pattern generating method, circuit designing method, test pattern generating program and circuit designing program A test pattern generating apparatus comprises a circuit data read in section 11 that divides circuit data into a plurality of functional blocks, a correspondence setting up table preparing section 12 that sorts the plurality of functional blocks into t... | 02/19/2008 |
| 7319936 | Instrument with interface for synchronization in automatic test equipment A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a re... | 01/15/2008 |
| 7315807 | System and methods for storage area network simulation A storage area network simulator, operable to simulate an exchange of calls emanating from a SAN management application to a plurality of manageable entities, allows analyzing SAN management application response to a particular configuration. A capture tool discover... | 01/01/2008 |
| 7299388 | Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer ch... | 11/20/2007 |
| 7283409 | Data monitoring for single event upset in a programmable logic device Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators... | 10/16/2007 |
| 7249296 | Semiconductor integrated circuit An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and writes/reads inverted data of the background data in at least a part of t... | 07/24/2007 |
| 7228470 | Semiconductor testing circuit, semiconductor storage device, and semiconductor testing method A semiconductor testing circuit being arranged for testing a semiconductor storage device, and having a simple construction and a great number of executable test patterns. Counters designate portions of a write/read address by count values outputted from the counter... | 06/05/2007 |
| 7187192 | Semiconductor test device having clock recovery circuit A semiconductor test device for acquiring a multiplexed clock signal from LSI output data and using the clock to test the LSI. The device includes a time interpolator and registers connected in series. The time interpolator has flip-flops connected in parallel for r... | 03/06/2007 |
| 7177222 | Reducing power consumption in a data storage system An apparatus and associated method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state refresh mode. A supply voltage level to the refresh load device is adjust... | 02/13/2007 |
| 7133999 | Method and system for local memory addressing in single instruction, multiple data computer system A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight ... | 11/07/2006 |
| 7120841 | Data generator for generating test data for word-oriented semiconductor memories A data generator for generating test data for a word-oriented semiconductor memory is integrated on a semiconductor chip of the semiconductor memory. The data generator has a shift register. ... | 10/10/2006 |
| 7114112 | Method, system, and program for simulating Input/Output (I/O) requests to test a system Provided are a method, system, and program for simulating I/O requests to test a system coupled to an adaptor having a port used for transmitting and receiving I/O requests to the system. A user test command is received indicating an I/O test object. The adaptor pro... | 09/26/2006 |
| 7106227 | Method and apparatus for synchronizing a multiple-stage multiplexer A method and apparatus for synchronizing multiple-stage multiplexers are disclosed. According to exemplary embodiments of the present invention, multiplexer circuits in the multiple-stage multiplexer are synchronized based upon a frequency response of the output of ... | 09/12/2006 |
| 7107166 | Device for testing LSI to be measured, jitter analyzer, and phase difference detector LSI test equipment can acquire output data of an LSI as a device under test by a clock signal output from the LSI to be measured and acquire measurement data synchronously with the output data having jitter. The LSI test equipment includes a clock side time interpol... | 09/12/2006 |
| 7103802 | System and method for testing computing devices An automated system for improving the testing of computer devices designed for coupling with docking devices. A plurality of networked computing devices that are individually connected to a compatible docking device through a slave switch. Each slave switch independ... | 09/05/2006 |
| 7103493 | Memory testing apparatus and method Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector,... | 09/05/2006 |
| 7103750 | Method and apparatus for finding repeated substrings in pattern recognition A method and apparatus for compressing a reference pattern (RP) with repeated substrings by encoding produce compressed reference patterns (CRPs) with reduce storage requirements. Operation codes and a flag are stored with the CRPs. During comparison of reference el... | 09/05/2006 |
| 7100098 | Systems and methods for testing performance of an electronic device A method for testing performance of a device-under-test (DUT) includes: examining vectors, each of the vectors including a plurality of characters; and creating waveform entries, each of the waveform entries corresponding to a distinct vector configuration encounter... | 08/29/2006 |
| 7072131 | Water marking in a data interval gap A storage device in which file data is divided into multiple blocks for storage on a recording medium. The storage device includes an additional data storing section for storing additional data to be recorded on the recording medium in association with the data to b... | 07/04/2006 |
| 7062697 | Pre-stored digital word generator A pre-stored digital word generator, more particularly, a digital word generator for providing multiple digital words. The pre-stored digital word generator includes a edge memory used to store a primary preset information; an edge address counter used to point to a... | 06/13/2006 |
| 7062392 | Configurable voltage regulator A voltage regulator has a plurality of predetermined configurations and comprises a measurement circuit to measure an electrical characteristic of at least one external impedance and to determine a digital value corresponding to the measured electrical characteristi... | 06/13/2006 |
| 7035154 | Semiconductor memory device and its test method as well as test circuit The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array 30. Then, a test signal TE1 ... | 04/25/2006 |
| 6996755 | Squence control circuit A sequence control circuit that is capable of operating at high-speed without using either a memory having a short access time or high-speed devices is provided. Each address of an instruction memory includes an instruction next to the current instruction designated... | 02/07/2006 |
| 6970794 | Semiconductor having reduced configuration pins and method thereof A configurable semiconductor device having a plurality of predetermined configurations comprises a measurement circuit to measure an electrical characteristic of at least one external impedance and to determine a digital value corresponding to the measured electrica... | 11/29/2005 |
| 6971055 | Method for verifying the accuracy of bit-map memory test programs A method for verifying the accuracy of bit-map memory test programs is disclosed, which employs a Focused Ion Beam (FIB) apparatus to make or break connections on one or more word lines or bit lines of the memory to be tested, causing abnormal data output from memor... | 11/29/2005 |
| 6964000 | Semiconductor integrated circuit device having a test circuit of a random access memory 32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits are input to 10 flip-flops serially arranged in an address shift regi... | 11/08/2005 |
| 6957373 | Address generator for generating addresses for testing a circuit An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group h... | 10/18/2005 |
