Bizarre Patents
A helium-filled sun shade for protecting individuals engaged in outdoor activities.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8074135 | Apparatus and method for testing and debugging an integrated circuit An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator performs a test on the integrated circuit. The embedded in-circuit emulator generates a testing result ba... | 12/06/2011 |
| 8046654 | Image data test unit, image apparatus having the same, and method of testing image data using the same An image data test unit includes a data acquisition unit configured to acquire image data having individual frames, an image data temporary storage unit configured to receive the acquired image data from the data acquisition unit to store a certain amount of the ima... | 10/25/2011 |
| 8001439 | Integrated circuit testing module including signal shaping interface Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit a... | 08/16/2011 |
| 7962823 | System and method for testing multiple packet data transmitters A system and method for testing a plurality of packet data transmitters in which multiple devices-under-test (DUTs) are tested by providing similar transmit data streams to the DUTs each of which, in response thereto, provides a respective packet data signal. At lea... | 06/14/2011 |
| 7958422 | Method and apparatus for generating self-verifying device scenario code Methods and systems for generating code for a device are disclosed. A device command for which the code is to be generated is selected. Response template parameters for the selected device commands are retrieved from a response template associated with the device co... | 06/07/2011 |
| 7941722 | Testing of integrated circuits using test module A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case into a memory using the DMLED test module, loading initialization signatures of fixed pattern into the memo... | 05/10/2011 |
| 7895493 | Bus failure management method and system A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The... | 02/22/2011 |
| 7890831 | Processor test system utilizing functional redundancy A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processo... | 02/15/2011 |
| 7844874 | Semiconductor integrated circuit device and inspection method therefor A semiconductor integrated circuit device includes: a plurality of devices under test formed on a substrate; a selection circuit formed on the substrate which selects two of the plurality of devices under test; a magnitude comparison circuit formed on the substrate ... | 11/30/2010 |
| 7774669 | Complex pattern generator for analysis of high speed serial streams The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traf... | 08/10/2010 |
| 7757143 | Semiconductor device including concealable test terminals A semiconductor device includes one or more test terminals and a test control circuit is disclosed. The test control circuit tests an internal circuit according to the signals received from the one or more test terminals. Afterwards, specification information held i... | 07/13/2010 |
| 7730376 | Providing high availability in a PCI-Express™ link in the presence of lane faults A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the fa... | 06/01/2010 |
| 7702984 | High volume testing for USB electronic data flash cards A high volume testing/formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the... | 04/20/2010 |
| 7661053 | Methods and apparatus for patternizing device responses A device response template generator software program includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses. The GUI enables patternization of the command response to that t... | 02/09/2010 |
| 7584395 | Systems, methods and apparatus for synthesizing state events for a test data stream In one embodiment, a method of has the steps of A) accessing a stream of test data comprising 1) a number of state events and 2) a number of data events interspersed with the ones of the state events; B) upon accessing one of the data events, determining if the data... | 09/01/2009 |
| 7559003 | Semiconductor memory test apparatus A semiconductor memory test apparatus has a log data generating unit for generating log data indicating a test result of a device under test based on output data from the device under test corresponding to a predetermined test pattern; and a log data storing unit fo... | 07/07/2009 |
| 7555690 | Device for and method of coupling test signals to a device under test Various embodiments of the present invention relate to a device for testing an integrated circuit. According to one embodiment, the device comprises a first connector coupled to receive a device under test and a second connector coupled to receive compressed test da... | 06/30/2009 |
| 7549100 | Dynamic verification traversal strategies A method of implementing a traversal strategy as part of a dynamic verification can include initializing a non-deterministic automaton (NDA) traversal mechanism that has (1) a strategy push-down stack (strategy PDS) that holds traversal strategy pointers and (2) an ... | 06/16/2009 |
| 7546507 | Method and apparatus for debugging semiconductor devices A tool for testing an integrated circuit is provided. The tool includes a vector execution engine, a vector image generation engine and a vector display engine. The vector execution engine applies test patterns to the integrated circuit and captures error data being... | 06/09/2009 |
| 7530000 | Early detection of storage device degradation An apparatus operable with a host and a data storage component for detecting a storage device susceptible to failure under I/O workload is provided. The apparatus includes a selector component for selecting a pair of storage devices in the data storage component. A ... | 05/05/2009 |
| 7478305 | Method and apparatus for interactive generation of device response templates and analysis A device response template generator software program includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses. The GUI allows patternization of the command response to that th... | 01/13/2009 |
| 7475318 | Method for testing the sensitive input range of Byzantine filters A Byzantine filter tester including a feedback loop, a pseudo random waveform generator and an output tester. The feedback loop is coupled between an output of a device under test and an input of the device under test. The feedback loop includes an odd number of inv... | 01/06/2009 |
| 7444574 | Stimulus extraction and sequence generation for an electric device under test A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block ... | 10/28/2008 |
| 7444565 | Re-programmable COMSEC module A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output fro... | 10/28/2008 |
| 7444575 | Architecture and method for testing of an integrated circuit device In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test cir... | 10/28/2008 |
| 7441169 | Semiconductor integrated circuit with test circuit A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for conne... | 10/21/2008 |
| 7437644 | Automatic self-testing of an internal device in a closed system A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system is automatically and periodically performed without triggering from ... | 10/14/2008 |
| 7437641 | Systems and methods for signature circuits Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in ... | 10/14/2008 |
| 7437629 | Method for checking the refresh function of an information memory A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these ... | 10/14/2008 |
| 7437635 | Testing hard-wired IP interface signals using a soft scan chain A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This “soft-wired” set of boundary scan registers can be used to test the interface connections between the IP core and the functional blocks of th... | 10/14/2008 |
| 7437638 | Boundary-Scan methods and apparatus Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to all of the drivers and hysteretic test receiver memories of a circuit... | 10/14/2008 |
| 7437262 | System and method for testing a device A system for testing a device includes a processor that operates to execute instructions, where the instructions are used to test a device. The processor also operates to generate test signals associated with the test instructions. An interface apparatus is coupled ... | 10/14/2008 |
| 7434120 | Test mode control circuit Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, ... | 10/07/2008 |
| 7430486 | Datalog support in a modular test system A method for communicating test information from a source to a destination is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, the at least one s... | 09/30/2008 |
| 7426668 | Performing memory built-in-self-test (MBIST) Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... | 09/16/2008 |
| 7426664 | Method for testing the error ratio of a device A method for testing the (Bit) Error Ratio BER of a device against a maximal allowable (Bit) Error Ratio BERlimit with a early pass and/or early fail criterion, whereby the early pass and/or early fail criterion is allowed to be wrong only by a small prob... | 09/16/2008 |
| 7424659 | System-in-package and method of testing thereof A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile ... | 09/09/2008 |
| 7421629 | Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to co... | 09/02/2008 |
| 7418639 | Test interface, system, and method for testing communications devices with non-deterministic latency A test interface is configured to connect to a testing device and a communications device. The communications device may be configured to receive a data signal (that includes a desired data portion) from the test machine. The interface may include a data capture dev... | 08/26/2008 |
| 7415649 | Semi-conductor component test device with shift register, and semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-condu... | 08/19/2008 |
