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| Number | Title | Issue Date |
| 7788565 | Semiconductor integrated circuit A semiconductor integrated circuit having a low maximum allowable operating frequency such as an analog circuit can be prevented from being destroyed during a scan test. When a scan test mode signal is “1”, output signals of a first AND circuit and a second AND ... | 08/31/2010 |
| 7761764 | System and method for self-test of integrated circuits A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal pro... | 07/20/2010 |
| 7694203 | On-chip samplers for asynchronously triggered events Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a trig... | 04/06/2010 |
| 7613974 | Fault detection method and apparatus This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and ... | 11/03/2009 |
| 7587648 | Integrated circuit having electrically isolatable test circuitry Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and powe... | 09/08/2009 |
| 7587647 | Method for testing analog and mixed-signal circuits using dynamic element matching for source linearization A method of testing an analog and/or mixed-signal circuit can be used in either a production or a built-in self test environment. The method includes generating an excitation signal for testing by using dynamic element matching for performance enhancement of the tes... | 09/08/2009 |
| 7451373 | Circuit for compression and storage of circuit diagnosis data A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test da... | 11/11/2008 |
| 7428683 | Automatic analog test and compensation with built-in pattern generator and analyzer A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test patter... | 09/23/2008 |
| 7405723 | Apparatus for testing display device and method for testing the same An apparatus for testing a display device includes a display device to display test patterns, a graphic process unit to supply analog mode signals and digital mode signals to the display device, and a control unit to allow test patterns of an analog testing mode and... | 07/29/2008 |
| 7373263 | Analog-type measurements for a logic analyzer A logic analyzer that performs analog-type measurements on digital data includes circuitry in its acquisition system that is programmable to search through acquired data to detect analog-type signal characteristics. In a first embodiment, the logic analyzer includes... | 05/13/2008 |
| 7372288 | Test apparatus for testing multiple electronic devices There is disclosed a test apparatus including a driver that outputs a test signal, a first switch that is provided between the driver and a terminal of the first device under test, a second switch that is provided between the driver and a terminal of the second devi... | 05/13/2008 |
| 7363568 | System and method for testing differential signal crossover using undersampling System and method for testing differential signal crossover in high-speed electronic equipment. A preferred embodiment comprises a test circuit coupled to a device under test (DUT) and an automatic test equipment (ATE). The test circuit comprises a pair of window co... | 04/22/2008 |
| 7348789 | Integrated circuit device with on-chip setup/hold measuring circuit An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The ... | 03/25/2008 |
| 7348913 | Arbitrary waveform generator, arbitrary waveform generate method, testing apparatus, and program There is provided an arbitrary waveform generator that generates an arbitrary waveform. The arbitrary waveform generator includes a waveform pattern generating section that generates pattern data showing a pattern of the arbitrary waveform, a digital-analog converti... | 03/25/2008 |
| 7343538 | Programmable multi-function module for automatic test equipment systems A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement ca... | 03/11/2008 |
| 7339389 | Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal In a semiconductor device, a main circuit is operated by a first clock signal, and at least one characteristic evaluating circuit is operated by a second clock signal whose frequency is higher than a frequency of the first clock signal. Also, at least one deteriorat... | 03/04/2008 |
| 7336212 | Apparatus and methods for measurement of analog voltages in an integrated circuit The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresp... | 02/26/2008 |
| 7327156 | LSI testing apparatus for testing an electronic device AN LSI testing apparatus includes a power source unit for supplying the direct source current to an electronic device, a detecting unit for detecting the source current supplied to the electronic device and a judging unit for judging the quality of the electronic de... | 02/05/2008 |
| 7323898 | Pin electronics driver Circuitry for driving a pin includes a first resistive circuit connected to the pin, a first transistor circuit to connect the first resistive circuit to a logic level voltage in response to a trigger voltage, the first transistor circuit and the first resistive cir... | 01/29/2008 |
| 7315971 | Systems and methods for improved memory scan testability A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input con... | 01/01/2008 |
| 7305601 | Method and test apparatus for testing integrated circuits using both valid and invalid test data A simplified boundary scan test method capable of performing boundary test scanning of semiconductor chips. The test method includes providing valid test data to a first terminal of the semiconductor device and purposely providing invalid test data to a second termi... | 12/04/2007 |
| 7296195 | Bit synchronization for high-speed serial device testing An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the center of the bit position. The strobe time adjustment is performed base... | 11/13/2007 |
| 7289286 | TMR/GMR amplifier with input current compensation An amplifier system with feedback current cancellation comprises an amplifier having at least one stage, a feedback network, first and second replica circuits, first and second unity-gain buffers, a second resistance, and a current mirror. The feedback network inclu... | 10/30/2007 |
| 7278079 | Test head utilized in a test system to perform automated at-speed testing of multiple gigabit per second high serial pin count devices A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external t... | 10/02/2007 |
| 7275197 | Testing apparatus A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes an operation order holding unit for holding information indicating that a test operation by... | 09/25/2007 |
| 7246288 | Integrated device with an improved BIST circuit for executing a structured test An integrated device including a functional circuitry and a built-in self testing circuit for executing a structured test on the functional circuitry is proposed. The functional circuitry includes means for receiving input test values from the built-in self testing ... | 07/17/2007 |
| 7245244 | Correction methods and structures for analog-to-digital converter transfer functions Methods and structures are provided to improve the transfer functions of analog-to-digital converter systems. They address the converter error function that corresponds to a converter's transfer function. In particular, they provide a corrector with a corrector tran... | 07/17/2007 |
| 7246289 | Memory integrity self checking in VT/TU cross-connect A method and apparatus for detecting errors in a memory includes generating a first check word based on incoming data and generating a second check word based on stored data. The method includes comparing the first check word to the second check word, generating a c... | 07/17/2007 |
| 7237168 | Design for test of analog module systems An apparatus for testing an integrated circuit that includes analog nodes is disclosed. In one aspect, an integrated circuit comprises testing circuitry and core logic circuitry. A memory in the testing circuitry stores data identifying analog nodes in the core logi... | 06/26/2007 |
| 7237167 | Testing apparatus A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes a first and a second testing modules, and a synchronization controlling unit. The synchroni... | 06/26/2007 |
| 7231306 | Method and apparatus for calibrating static timing offsets across multiple outputs Methods and apparatuses for calibrating out static timing offsets across multiple outputs of a transmitting device are provided. In accordance with at least one embodiment, a signal is selected as the master reference signal, and a closed-loop feedback system is pro... | 06/12/2007 |
| 7228479 | IEEE Std. 1149.4 compatible analog BIST methodology An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quant... | 06/05/2007 |
| 7222281 | Test head utilized in a test system to perform automated at-speed testing of multiple gigabit per second high serial pin count devices A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external t... | 05/22/2007 |
| 7222261 | Automatic test equipment for design-for-test (DFT) and built-in-self-test circuitry An analog/mixed-signal DFT/BIST test module for use in a semiconductor tester to support DFT/BIST testing of semiconductor devices having at least one analog/mixed-signal circuit-under-test is disclosed. The analog/mixed-signal circuit-under-test coupled to an on-ch... | 05/22/2007 |
| 7219283 | IC with TAP, STP and lock out controlled output buffer Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. A first buffer has an input connected to a scan output lead, a control input, and an ou... | 05/15/2007 |
| 7219270 | Device and method for using a lessened load to measure signal skew at the output of an integrated circuit A device and method are provided for testing the timing of an output signal from a circuit. The output signal can be sent from a circuit contained within a portion of an integrated circuit, and represents a response to a test pattern or stimuli applied to that circu... | 05/15/2007 |
| 7197683 | Digital-to-analog conversion with an interleaved, pulse-width modulated signal The invention relates to a method and a circuit for digital-to-analog conversion, in which an interleaved pulse-width modulation signal (VPWM) is low-pass-filtered. ... | 03/27/2007 |
| 7178079 | Reception data synchronizing apparatus and method, and recording medium with recorded reception data synchronizing program A synchronism pattern detecting timing recorder (20) records a synchronism pattern detecting timing at which a synchronism pattern is detected in reception data, a synchronism decider (12) collates the reception data with reference data to decide wheth... | 02/13/2007 |
| 7124341 | Integrated circuit having electrically isolatable test circuitry Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and powe... | 10/17/2006 |
| 7113882 | Automatic testing system An automatic testing system. A sampling and converting device obtains a plurality of electronic parameters from a tested device and transforms them into a plurality of digital signals. A microprocessor receives the digital signals and performs various short-circuit ... | 09/26/2006 |
