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| Number | Title | Issue Date |
| 8127192 | Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store in... | 02/28/2012 |
| 7900111 | Method and apparatus for random stimulus generation Capabilities are added to a Hardware Verification Language that facilitates the generation of test data. Random number sources, called random variables, can be produced by adding a randomness attribute to a variable declaration of a class definition. A “randomize... | 03/01/2011 |
| 7895492 | Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum c... | 02/22/2011 |
| 7865794 | Decompressor/PRPG for applying pseudo-random and deterministic test patterns A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decom... | 01/04/2011 |
| 7765450 | Methods for distribution of test generation programs As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be co... | 07/27/2010 |
| 7757142 | Self-synchronizing pseudorandom bit sequence checker Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In... | 07/13/2010 |
| 7743306 | Test vector generating method and test vector generating program of semiconductor logic circuit device The X-type of each bit permutation is determined (step 301). When there are X-types except for X-type 1, i.e., X-type with no don't-care bits, total capture state transition numbers TECTA1 and TECTA2 for capture clock pulses C | 06/22/2010 |
| 7653855 | Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the ran... | 01/26/2010 |
| 7454680 | Method, system and computer program product for improving efficiency in generating high-level coverage data for a circuit-testing scheme A method, system and computer program product for generating a coverage model to describe a testing scheme for a simulated system are described. In a preferred embodiment, a simulated system is tested with a testing simulation program. A simple event database is gen... | 11/18/2008 |
| 7444558 | Programmable measurement mode for a serial point to point link A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and ... | 10/28/2008 |
| 7441172 | DVI link with parallel test data An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer ... | 10/21/2008 |
| 7437261 | Method and apparatus for testing integrated circuits A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of one or more site controllers by a system controller. One or more local... | 10/14/2008 |
| 7424417 | System and method for clock domain grouping using data path relationships A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of ea... | 09/09/2008 |
| 7421629 | Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to co... | 09/02/2008 |
| 7421637 | Generating test input for a circuit Generating test input includes initializing a current pseudo-random value at a test input generator coupled to a circuit component. Write data is received from the circuit component. The following are repeated to generate next pseudo-random values as test input. The... | 09/02/2008 |
| 7415649 | Semi-conductor component test device with shift register, and semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-condu... | 08/19/2008 |
| 7415648 | Method and system for testing a network interface A method for testing a network interface is provided that includes generating a data pattern file based on a pseudocode file and testing the interface using the data pattern file. The pseudocode file defines an order for a plurality of data patterns in the data patt... | 08/19/2008 |
| 7412640 | Self-synchronizing pseudorandom bit sequence checker Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In... | 08/12/2008 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 7395478 | Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a f... | 07/01/2008 |
| 7386776 | System for testing digital components In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from... | 06/10/2008 |
| 7373550 | Generation of a computer program to test for correct operation of a data processing apparatus Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to ... | 05/13/2008 |
| 7370296 | Modeling language and method for address translation design mechanisms in test generation Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is r... | 05/06/2008 |
| 7366952 | Interconnect condition detection using test pattern in idle packets In some embodiments, a receiver can receive from an interconnect information packets and idle packets, where one or more of the idle packets includes a test pattern. A condition detector can detect a condition of the interconnect in response to the test pattern. Oth... | 04/29/2008 |
| 7366651 | Co-simulation interface Method and apparatus for interfacing between a high-level modeling system and a hardware description language (HDL) co-simulation engine. A plurality of HDL co-simulation engine libraries are queried as to the capabilities of the engines. A co-simulation engine is s... | 04/29/2008 |
| 7367001 | Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intend... | 04/29/2008 |
| 7366650 | Software and hardware simulation A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respecti... | 04/29/2008 |
| 7363567 | System and method for electronic device testing using random parameter looping Disclosed is a system and method for testing electronic devices which uses a random pattern for testing electronic devices. In one embodiment there is communicated to a device under test (DUT) a test sequence causing the DUT to exercise certain parameters in a contr... | 04/22/2008 |
| 7360184 | Method and apparatus for scenario search based random generation of functional test suites A method of describing a set of tests capable of being performed on a device under test (DUT) is disclosed. The method includes identifying a scenario space of the DUT. ... | 04/15/2008 |
| 7359847 | Tracking converage results in a batch simulation farm network A method and system for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation ... | 04/15/2008 |
| 7360127 | Method and apparatus for evaluating and optimizing a signaling system A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive... | 04/15/2008 |
| 7360138 | Verification of the design of an integrated circuit background A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated value... | 04/15/2008 |
| 7356786 | Method and user interface for debugging an electronic system Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with... | 04/08/2008 |
| 7353284 | Synchronized transmission of audio and video data from a computer to a client via an interface A method for controlling data transmission between a computer and a video client via an interface, the method comprising: the computer polling the interface a first time to determine the size of the buffer on the interface; receiving a first buffer size value from t... | 04/01/2008 |
| 7350109 | System and method for testing a memory using DMA A computer system that includes a processor, a first bus coupled to the processor, a memory controller coupled to the first bus, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the first bus, and a test module coupled to t... | 03/25/2008 |
| 7343538 | Programmable multi-function module for automatic test equipment systems A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement ca... | 03/11/2008 |
| 7343533 | Hub for testing memory and methods thereof A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based on received memory control information and to write the pseudo random... | 03/11/2008 |
| 7333518 | Transmission method and transmission system as well as communications device A transmission method according to the present invention is capable of transmitting and receiving a data signal and information signal among a plurality of devices by full-duplex operation, wherein, when the information signal consecutively repeats a single pattern,... | 02/19/2008 |
| 7330320 | Method and apparatus to limit DC-level in coded data In a perpendicular magnetic recording system, the data that is being written by the write channel is fed back into the read channel. The read channel processes the data and decides if the written sequence is likely to have very poor DC characteristics. If that is th... | 02/12/2008 |
| 7325182 | Method and circuit arrangement for testing electrical modules The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The c... | 01/29/2008 |
