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| Number | Title | Issue Date |
| 8166361 | Integrated circuit testing module configured for set-up and hold time testing Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameter... | 04/24/2012 |
| 8161338 | Modular compaction of test responses Exemplary embodiments of a compactor for compacting test responses are disclosed. In certain embodiments, the compactor comprises circular registers and has multiple inputs. The circular registers can have lengths that are relatively prime or prime. In certain imple... | 04/17/2012 |
| 8156395 | Methods for generating test patterns for sequential circuits A single-pass method for test pattern generation for sequential circuits employs a local-fault at each time-frame. The result is that a fault arriving at circuit primary output lines unambiguously signals the discovery of a valid test pattern sequence for the fault.... | 04/10/2012 |
| 8086925 | Method and system for LBIST testing of an electronic circuit A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset range of LBIST patterns from a plurality of LBIST patterns arranged in an order, wherein each LBIST pattern of... | 12/27/2011 |
| 8074134 | Pattern generator and memory testing device using the same An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that inclu... | 12/06/2011 |
| 8055968 | Panel driving circuit that generates panel test pattern and panel test method thereof A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test dat... | 11/08/2011 |
| 8051352 | Timing-aware test generation and fault simulation Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In ... | 11/01/2011 |
| 8046653 | Low power decompression of test cubes Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a vari... | 10/25/2011 |
| 8037387 | Conversion device, conversion method, program, and recording medium Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constit... | 10/11/2011 |
| 8028213 | Data transformation method and related device for a testing system A data transformation method for a testing system includes using a reception end for receiving a test signal comprising a test data and a timing information corresponding to the test data, and using a transformation unit for transforming the test data according to t... | 09/27/2011 |
| 8006155 | Testing an operation of integrated circuitry A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for:... | 08/23/2011 |
| 8001437 | Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test patterns with expected responses, the method including: ... | 08/16/2011 |
| 7987402 | Semiconductor memory device having burn-in test mode and method for driving the same A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting con... | 07/26/2011 |
| 7984353 | Test apparatus, test vector generate unit, test method, program, and recording medium Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a vector selecting section that selects test vectors that cause a prescribed characteristic of the device under... | 07/19/2011 |
| 7979765 | Generating device, generating method, program and recording medium Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (... | 07/12/2011 |
| 7971118 | Conversion device, conversion method, program, and recording medium Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vec... | 06/28/2011 |
| 7962822 | Generating device, generating method, program and recording medium A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatu... | 06/14/2011 |
| 7958421 | Single-pass, concurrent-validation methods for generating test patterns for sequential circuits A single-pass, concurrent validation method for generating test pattern sequences for sequential circuits maps fault objects arriving at circuit next-state lines into good next-state fault objects, and passes these mapped results to a next time-frame by placing the ... | 06/07/2011 |
| 7954031 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/31/2011 |
| 7949923 | Test entry circuit and method for generating test entry signal Test entry circuit and method for generating test entry signal including a first source signal generator configured to receive a test signal through a pad to generate a first mode source signal for a first test mode, a second source signal generator configured to co... | 05/24/2011 |
| 7949922 | Test apparatus, shift amount measuring apparatus, shift amount measuring method and diagnostic method A shift amount measuring apparatus for measuring a phase shift amount of a signal under measurement which is input thereto includes a PLL circuit that generates a strobe signal which is synchronized with a reference signal, a CDR circuit that inputs, into the PLL ci... | 05/24/2011 |
| 7934136 | Test apparatus, pattern generator, test method and pattern generating method Provided is a test apparatus for testing a specimen by using a test pattern and an expected value pattern. The test apparatus includes: a control unit for outputting a test pattern to the specimen; a pattern converting unit for converting the expected value pattern ... | 04/26/2011 |
| 7917825 | Method and apparatus for selectively utilizing information within a semiconductor device Embodiments of the present invention include an apparatus to selectively provide information within a device to enable the device to perform a function. The apparatus comprises a generator unit to generate information for the device to perform the function, a receiv... | 03/29/2011 |
| 7890830 | Test signal generating apparatus The present invention is to provide a test signal generating apparatus which can generate a test signal for testing a device that dynamically change its operational state in response to a signal or the like. The test signal generating apparatus includes: a pattern s... | 02/15/2011 |
| 7865793 | Test case generation with backward propagation of predefined results and operand dependencies A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structu... | 01/04/2011 |
| 7853850 | Testing hardware components to detect hardware failures A system for testing hardware components includes a test pattern injector and a test pattern detector coupled to verification paths that pass through hardware components. The test pattern injector generates unique test patterns. A test pattern tests hardware feature... | 12/14/2010 |
| 7853849 | High-speed serial transfer device test method, program, and device A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according to a code conversion table are successively transferred to each of a plurality of serial transfer channels ... | 12/14/2010 |
| 7788564 | Adjustable test pattern results latency A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configur... | 08/31/2010 |
| 7774668 | System and method for detecting non-reproducible pseudo-random test cases A method for monitoring a test case generator system by detecting non-reproducible pseudo-random test cases, comprising: building a first pseudo-random test case having a first sequence of seeds comprising a first starting seed and a first ending seed through the te... | 08/10/2010 |
| 7765449 | Test apparatus that tests a plurality of devices under test having plural memory cells and test method therefor A test apparatus that tests a plurality of device under tests includes: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; an additional pattern storage section that p... | 07/27/2010 |
| 7743305 | Test apparatus, and electronic device A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation contro... | 06/22/2010 |
| 7743304 | Test system and method for testing electronic devices using a pipelined testing architecture A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test contr... | 06/22/2010 |
| 7739572 | Tester for testing semiconductor device A tester for testing a semiconductor device is disclosed. The tester for testing the semiconductor device employs a data selector for converting a logical test pattern data transmitted from a pattern generator into a physical test pattern data and an expected data b... | 06/15/2010 |
| 7725793 | Pattern generation for test apparatus and electronic device There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequ... | 05/25/2010 |
| 7707473 | Integrated testing apparatus, systems, and methods Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test re... | 04/27/2010 |
| 7694202 | Providing memory test patterns for DLL calibration A system and method to provide memory test patterns for the calibration of a delay locked loop (DLL) using a pseudo random bit sequence (PRBS) stored in a serial presence detect (SPD) circuit memory. The test bits stored in the SPD memory are transferred to a memory... | 04/06/2010 |
| 7689886 | System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address... | 03/30/2010 |
| 7685491 | Test generation methods for reducing power dissipation and supply currents Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In ... | 03/23/2010 |
| 7673209 | Test pattern generating circuit and semiconductor memory device having the same Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a ... | 03/02/2010 |
| 7669101 | Methods for distributing programs for generating test data Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed i... | 02/23/2010 |
