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| Number | Title | Issue Date |
| 7996742 | Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement A circuit arrangement comprising a logic circuit to be tested and a test circuit. The logic circuit comprising logic-circuit-internal combinations configured to generate output data from input data based on a predetermined relationship. The logic circuit is configur... | 08/09/2011 |
| 7873891 | Programmable voltage divider A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The pr... | 01/18/2011 |
| 7827455 | System and method for detecting glitches on a high-speed interface The current invention provides a mechanism for detecting and recovering from glitches on data strobes. In one embodiment, data is captured from an interlace by a receiver using at least one data strobe that is provided by the transmitter along with the data. A write... | 11/02/2010 |
| 7673207 | Method for at speed testing of devices A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detect... | 03/02/2010 |
| 7634702 | Integrated circuit apparatus having improved test circuit and method of testing the integrated circuit apparatus An integrated circuit apparatus including an improved test circuit and a method of testing the integrated circuit apparatus are provided. The integrated circuit apparatus determines pass or fail of the integrated circuit apparatus itself by comparing internal DQ dat... | 12/15/2009 |
| 7536620 | Method of and apparatus for validation support, computer product for validation support An information input unit inputs functional configuration information representing a function of a device to be validated. A condition input unit inputs conditions concerning input/output sequence that is given to the device. A function generation unit generates a v... | 05/19/2009 |
| 7526702 | Method and system for testing a random access memory (RAM) device having an internal cache A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, the method comprising: writing a value to an address in the RAM device, the value being stored i... | 04/28/2009 |
| 7447964 | Difference signal path test and characterization circuit A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The pr... | 11/04/2008 |
| 7444559 | Generation of memory test patterns for DLL calibration A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system dat... | 10/28/2008 |
| 7444565 | Re-programmable COMSEC module A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output fro... | 10/28/2008 |
| 7434114 | Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training se... | 10/07/2008 |
| 7433793 | Error detection apparatus and method and signal extractor A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through th... | 10/07/2008 |
| 7428679 | Method for automated at-speed testing of high serial pin count multiple gigabit per second devices A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first sign... | 09/23/2008 |
| 7426668 | Performing memory built-in-self-test (MBIST) Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... | 09/16/2008 |
| 7409631 | Error-detection flip-flop An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a ... | 08/05/2008 |
| 7408362 | Electronic package and method for testing the same An integrated circuit package includes at least two electronic circuits. A first of the at least two electronic circuits includes a digital input and a digital output and a test mode control line for setting the first integrated circuit chip into a determined test m... | 08/05/2008 |
| 7401276 | Semiconductor device with test circuit and test method of the same A semiconductor device includes an output path; an input path; and a test signal generating circuit. The test signal generating circuit generates an input test data signal by changing at least one of an amplitude and a phase of an output test data signal which is ge... | 07/15/2008 |
| 7398351 | Method and system for controlling access to data of a tape data storage medium using encryption/decryption of metadata A method, system, and machine-readable medium for controlling access to data of a tape data storage medium are disclosed. In accordance with one embodiment, a method is provided which comprises conveying data access control metadata from a tape cartridge comprising ... | 07/08/2008 |
| 7376889 | Memory device capable of detecting its failure A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data inp... | 05/20/2008 |
| 7372916 | Process and devices for transmitting digital signals over buses and computer program product therefore Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be ... | 05/13/2008 |
| 7370237 | Semiconductor memory device capable of accessing all memory cells A semiconductor memory device according to embodiments of the invention includes N channels for interface with an outside. During a test mode where the semiconductor memory device is tested by a tester having M channels, K ones of the N channels of the memory device... | 05/06/2008 |
| 7363565 | Method of testing apparatus having master logic unit and slave logic unit An apparatus which is tested includes a master logic unit and a slave logic unit. The testing method includes accessing a virtual slave logic unit by a test pattern which includes an address for accessing and an expected value of a waiting time, returning a response... | 04/22/2008 |
| 7363567 | System and method for electronic device testing using random parameter looping Disclosed is a system and method for testing electronic devices which uses a random pattern for testing electronic devices. In one embodiment there is communicated to a device under test (DUT) a test sequence causing the DUT to exercise certain parameters in a contr... | 04/22/2008 |
| 7360127 | Method and apparatus for evaluating and optimizing a signaling system A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive... | 04/15/2008 |
| 7353162 | Scalable reconfigurable prototyping system and method A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customiz... | 04/01/2008 |
| 7353430 | Device for validating an integrated circuit A device (10) for validating a circuit (1) comprising at least one microprocessor (3) and a specialized unit (2) provided with registers includes a base (11) for receiving the circuit, a memory (4, 5) simulating an external ... | 04/01/2008 |
| 7336749 | Statistical margin test methods and circuits Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique ... | 02/26/2008 |
| 7334174 | Semiconductor integrated circuit device and error detecting method therefor A semiconductor integrated circuit device includes a programmable circuit in which information is programmed, an information holding circuit which electrically holds information programmed in the programmable circuit, a compression circuit which compresses informati... | 02/19/2008 |
| 7331006 | Multiple sweep point testing of circuit devices An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part... | 02/12/2008 |
| 7330502 | Input/output circuit and semiconductor integrated circuit An input/output circuit includes a reference clock generator configured to generate a reference clock. A signal transmitter is configured to transmit serial data in synchronization with one of the reference clock and a test clock. A signal-receiving circuit is confi... | 02/12/2008 |
| 7330383 | Semiconductor device with a plurality of fuse elements and method for programming the device A device and method for programming the semiconductor device that includes a plurality of first fuse-sets which store first information, wherein each of the first fuse-sets includes at least one first fuse element and the first information has been compressed, a sec... | 02/12/2008 |
| 7325176 | System and method for accelerated information handling system memory testing Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instanc... | 01/29/2008 |
| 7313037 | RFID system including a memory for correcting a fail cell and method for correcting a fail cell using the same A radio frequency identification (RFID) system and a method for correcting a failed cell using the same are provided. The RFID system effectively corrects randomly distributed cell data by using a failed cell correcting circuit in a memory. In the RFID system, a pre... | 12/25/2007 |
| 7284169 | System and method for testing write strobe timing margins in memory devices Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a tra... | 10/16/2007 |
| 7260503 | Testing using policy-based processing of test results A testing technique and apparatus are described for apply a test to a System Under Test (SUT) in one or more configurations of the SUT. The test can generate and store multiple output results that capture the behavior of the SUT in performing the test. Policy analys... | 08/21/2007 |
| 7257754 | Semiconductor memory device and test pattern data generating method using the same A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting... | 08/14/2007 |
| 7257759 | Accounting for error carryover in error correction on M-bit encoded links 64/66b encoding (IEEE 802.3ae Standard for 10 Gigabit Ethernet) is based on a self-synchronous scrambler which inherently duplicates errors occurring in the transmission line. An error carryover indicator ECI vector is used to correct duplicated errors crossing the ... | 08/14/2007 |
| 7254764 | Generating test patterns used in testing semiconductor integrated circuit Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated by sim... | 08/07/2007 |
| 7254759 | Methods and systems for semiconductor defect detection A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a s... | 08/07/2007 |
| 7243283 | Semiconductor device with self-test circuits and test method thereof A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor devi... | 07/10/2007 |
