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| Number | Title | Issue Date |
| 8055967 | TAP interface outputs connected to TAP interface inputs An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. ... | 11/08/2011 |
| 8051351 | DDR circuit with addressable TAP linking circuitry and plural TAPS A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from th... | 11/01/2011 |
| 8020059 | Tap and control with data I/O, TMS, TDI, and TDO An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the avail... | 09/13/2011 |
| 7954030 | Automatable scan partitioning for low power using external control Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of... | 05/31/2011 |
| 7913142 | Method for testing at least one arithmetic unit installed in a control unit A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithm... | 03/22/2011 |
| 7870455 | System-on-chip with master/slave debug interface A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug int... | 01/11/2011 |
| 7823038 | Connecting analog response to separate strobed comparator input on IC Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and powe... | 10/26/2010 |
| 7810004 | Integrated circuit having a subordinate test interface An integrated circuit having a subordinate test interface and method for transmitting digital data is disclosed. The integrated circuit includes at least one test interface that is adapted to write and read data in and from a data memory, the at least one test inter... | 10/05/2010 |
| 7802160 | Test apparatus and calibration method A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the r... | 09/21/2010 |
| 7694201 | Semiconductor testing device having test result sending back to generate second data A semiconductor testing device includes: a data memory which stores a test program, said test program generating a test command for testing a plurality of functions within one function area of a plurality of function areas of a semiconductor device, said test comman... | 04/06/2010 |
| 7661051 | System to reduce programmable range specifications for a given target accuracy in calibrated electronic circuits An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circu... | 02/09/2010 |
| 7610538 | Test apparatus and performance board for diagnosis A test apparatus being capable of replacing a test module with the other kind of test module that tests device under tests by using the test module is provided. The test apparatus includes a plurality of test modules that transmit/receive signals to/from the device ... | 10/27/2009 |
| 7581152 | Fault free store data path for software implementation of redundant multithreading environments A method for a fault free store data path in a software implementation of redundant multithreading environments is described. In one embodiment, after a check is performed by a hardware/software checker, the processor still needs to ensure that the data just checked... | 08/25/2009 |
| 7529999 | Integrated circuit arrangement and method An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled ... | 05/05/2009 |
| 7526701 | Method and apparatus for measuring group delay of a device under test A method of measuring group delay of a device under test is provided. The method includes the steps of providing an analog input signal with a predetermined period to the device under test to obtain a delayed output signal from the device under test, converting the ... | 04/28/2009 |
| 7519890 | Input/output circuit for handling unconnected I/O pads A method based on a circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a ... | 04/14/2009 |
| 7496819 | Custom logic BIST for memory controller A method and system for testing a memory controller are provided herein. A test sequence may be generated within the memory controller. A test output may also be generated within the memory controller, where the test output is associated with the test sequence. The ... | 02/24/2009 |
| 7478302 | Signal integrity self-test architecture A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module, wherein the at least one module incorporates at least one associated module monitor suitable for monitoring a device parameter such as temperature, su... | 01/13/2009 |
| 7478303 | System and method for testing nodes in a network A method and system for testing nodes in a network, where the network includes a plurality of nodes and at least one bus for coupling the plurality of nodes. The system includes a control processor for generating test commands to be sent to at least one node of the ... | 01/13/2009 |
| 7475316 | System, method and storage medium for providing a high speed test interface to a memory subsystem A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow sp... | 01/06/2009 |
| 7444571 | Apparatus and method for testing and debugging an integrated circuit A system for testing a target integrated circuit comprises a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the integrated circuit and that analyzes received data from the target integrated circuit. A... | 10/28/2008 |
| 7444558 | Programmable measurement mode for a serial point to point link A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and ... | 10/28/2008 |
| 7444573 | VLCT programmation/read protocol An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address spec... | 10/28/2008 |
| 7441169 | Semiconductor integrated circuit with test circuit A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for conne... | 10/21/2008 |
| 7441165 | Read-only memory and operational control method thereof A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data st... | 10/21/2008 |
| 7437644 | Automatic self-testing of an internal device in a closed system A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system is automatically and periodically performed without triggering from ... | 10/14/2008 |
| 7437635 | Testing hard-wired IP interface signals using a soft scan chain A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This “soft-wired” set of boundary scan registers can be used to test the interface connections between the IP core and the functional blocks of th... | 10/14/2008 |
| 7437626 | Efficient method of test and soft repair of SRAM with redundancy Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant e... | 10/14/2008 |
| 7434120 | Test mode control circuit Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, ... | 10/07/2008 |
| 7428674 | Monitoring the state vector of a test access port Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitor... | 09/23/2008 |
| 7428682 | Semiconductor memory device In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and ... | 09/23/2008 |
| 7426668 | Performing memory built-in-self-test (MBIST) Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... | 09/16/2008 |
| 7424657 | Method and device for testing an integrated circuit, integrated circuit to be tested, and wafer with a large number of integrated circuits to be tested A method and a device for testing an integrated circuit are defined by the fact that the testing of the integrated circuit is begun by a self-test device contained in the integrated circuit before the integrated circuit is connected to an external testing device tha... | 09/09/2008 |
| 7424660 | Synchronization point across different memory BIST controllers A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An ou... | 09/09/2008 |
| 7421384 | Semiconductor integrated circuit device and microcomputer development supporting device During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits i... | 09/02/2008 |
| 7421633 | Controller receiving combined TMS/TDI and suppyling separate TMS and TDI An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the avail... | 09/02/2008 |
| 7421629 | Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to co... | 09/02/2008 |
| 7421365 | Automated circuit board test actuator system An apparatus for automatically inserting connectors and coupling test probes to circuit boards, such as computer system boards and the like. The apparatus enables connectors to be automatically inserted into mating connectors on a circuit board device under test (DU... | 09/02/2008 |
| 7418643 | Integrated circuit having electrically isolatable test circuitry Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and powe... | 08/26/2008 |
| 7418642 | Built-in-self-test using embedded memory and processor in an application specific integrated circuit A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern f... | 08/26/2008 |
