Class 714/733 - Built-in testing circuit (BILBO)

Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter in which the digital logic testing equipment
No. of patents: 1481
Last issue date: 04/10/2012

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Number	Title	Issue Date
8156394	Selectively accessing test access ports in a multiple test access port environment A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ...	04/10/2012
8140926	Die selectively connecting TAP leads to second die An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. ...	03/20/2012
8127191	Control method for semiconductor integrated circuit and semiconductor integrated circuit A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during...	02/28/2012
8122312	Internally controlling and enhancing logic built-in self test in a multiple core microprocessor A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while a...	02/21/2012
8117512	Failure detection and mitigation in logic circuits The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a...	02/14/2012
8112686	Deterministic logic built-in self-test stimuli generation Techniques for storing and using compressed restrict values for selected scan chains and flip-flops, such that the states that need to be applied to those flip flops need not be solved by a linear equation system solver, such as a linear equation system solver provi...	02/07/2012
8108744	Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main contr...	01/31/2012
8082477	Method of memory build-in self-test The present invention discloses a memory build-in self-test comprising steps of: (a) determining whether there is redundant address in the ROM; (b) when there is redundant address for storing standard check code, transferring the coefficient file in the ROM to a pre...	12/20/2011
8069386	Semiconductor device A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and...	11/29/2011
8055966	Built-in-self-repair arrangement for a single multiple-integrated circuit package and methods thereof A multiple integrated circuit arrangement within a single package is provided. The multiple integrated circuit arrangement includes a set of electronic components, which includes at least a set of dies. The first die of the set of dies is coupled to a first electron...	11/08/2011
8051350	Serial interface device built-in self test A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer....	11/01/2011
8046652	Built-in self-test using embedded memory and processor in an application specific integrated circuit A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern f...	10/25/2011
8037386	TAP with select output from one of IR and DR A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ...	10/11/2011
8028212	Parallel scan paths with header data circuitry and header return circuitry Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan f...	09/27/2011
8028211	Look-ahead built-in self tests with temperature elevation of functional elements A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, elevating the temp...	09/27/2011
8024632	Method and mechanism for implementation-independent, on-line, end-to-end detection of faults in self-checking queues in digital hardware systems A method and apparatus are provided for detecting faults in a queue (also known as FIFO) in a digital system. The method augments the FIFO with an external monitoring mechanism which, on demand, checks the FIFO's operation and alerts the system to malfunctioning of ...	09/20/2011
8006153	Multiple uses for BIST test latches A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built...	08/23/2011
8001434	Memory board with self-testing capability A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devi...	08/16/2011
8001435	Register selection circuitry receiving select signals from test interfaces A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ...	08/16/2011
8001436	Changing scan paths shifting by changing mode select input state Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from re...	08/16/2011
7984352	Saving debugging contexts with periodic built-in self-test execution A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. ...	07/19/2011
7971116	Semiconductor storage device and test method therefor Disclosed is a semiconductor device including a BIST provided with a plurality of scan FFs (flip-flops), a data address signal generation circuit unit which respectively generates a data signal and an address signal based on a set value of a scan FF, WEB generation ...	06/28/2011
7962821	Built-in self testing circuit with fault diagnostic capability A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure det...	06/14/2011
7954028	Structure for redundancy programming of a memory device A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuits for implementing a method wherein it is assumed that all fails are r...	05/31/2011
7954029	System, apparatus, and method for memory built-in self testing using microcode sequencers Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on ...	05/31/2011
7937636	Semiconductor device and inspection method of semiconductor device and wireless chip The invention provides an inspection method of a semiconductor device which receives a test program wirelessly. As an inspection method of the semiconductor device, a test program is transmitted as a communication signal for every test. By transmitting a test progra...	05/03/2011
7937637	TAP with enable input gated and multiplexed mode select A TAP Linking Module (TLM) couples plural TAPs, via select and enable signals, to an externally accessible IEEE 1149.1 interface. The select signals are outputs from the TAPs to the TLM, and the enable signals are output from the TLM to the TAPs. Each select signal ...	05/03/2011
7934134	Method and apparatus for performing logic built-in self-testing of an integrated circuit A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logic...	04/26/2011
7934135	Providing pseudo-randomized static values during LBIST transition tests An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions t...	04/26/2011
7928750	Contactless interfacing of test signals with a device under test An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test...	04/19/2011
7925949	Embedded processor Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction wi...	04/12/2011
7925951	Scan circuitry controlled switch connecting buffer output to test lead The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die. ...	04/12/2011
7925950	Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic m...	04/12/2011
7921346	Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD) A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target ...	04/05/2011
7921345	Automated test system A system comprising a plurality of components and an automation module coupled to the plurality of components. The automation module is adapted to automatically initialize a software test environment for at least one of the plurality of components, where the softwar...	04/05/2011
7913141	Power gating in integrated circuits for leakage reduction A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power suppl...	03/22/2011
7908538	Failure prediction circuit and method, and semiconductor integrated circuit Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and...	03/15/2011
7900110	Optimized JTAG interface An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the avail...	03/01/2011
7900109	BDX data in stable states A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring ...	03/01/2011
7895491	Integrated circuit with low-power built-in self-test logic An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern of data into the loading circuit without powering the combinational...	02/22/2011

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Class 714/733 - Built-in testing circuit (BILBO)