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| Number | Title | Issue Date |
| 8112685 | Serial compressed data I/O in a parallel test compression architecture The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Furthe... | 02/07/2012 |
| 8108743 | Method and apparatus for selectively compacting test responses A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to t... | 01/31/2012 |
| 8060800 | Evaluation circuit and method for detecting and/or locating faulty data words in a data stream T An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in para... | 11/15/2011 |
| 7996741 | Method and apparatus for low-pin-count scan compression A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells co... | 08/09/2011 |
| 7962820 | Fault diagnosis of compressed test responses Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is r... | 06/14/2011 |
| 7930610 | System and method for power reduction through power aware latch weighting of complex sub-circuits A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logi... | 04/19/2011 |
| 7925947 | X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns A method and apparatus for compacting test responses containing unknown (X) values in a scan-based integrated circuit using an X-canceling multiple-input signature register (MISR) to produce a known (non-X) signature. The known (non-X) signature is obtained by selec... | 04/12/2011 |
| 7925948 | System and method for power reduction through power aware latch weighting A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a we... | 04/12/2011 |
| 7913140 | Method and device to detect failure of static control signals A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one... | 03/22/2011 |
| 7904775 | Microprocessor comprising signature means for detecting an attack by error injection A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or d... | 03/08/2011 |
| 7895490 | Method and system for testing an electronic circuit to identify multiple defects A method for testing an electronic circuit comprises selecting a plurality of test patterns arranged in an order. The method tests an electronic circuit by applying to the electronic circuit a first subset range of the plurality of test patterns sequentially in the ... | 02/22/2011 |
| 7890827 | Compressing test responses using a compactor The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover,... | 02/15/2011 |
| 7873890 | Techniques for performing a Logic Built-In Self-Test in an integrated circuit device A method, system and computer program product for performing device characterization Logic Built-In Self-Test (LBIST) in an IC device. Test parameters of the LBIST are saved in a memory of the IC device, and nominal operational parameters of the IC device are used t... | 01/18/2011 |
| 7870453 | Circuit arrangement and method of testing an application circuit provided in said circuit arrangement According to an example embodiment, there is an integrated circuit arrangement with at least one application circuit to be tested, and with at least one self-test circuit for testing the application circuit and generating at least one pseudo-random test sample. wher... | 01/11/2011 |
| 7856582 | Techniques for logic built-in self-test diagnostics of integrated circuit devices A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded v... | 12/21/2010 |
| 7853848 | System and method for signature-based systematic condition detection and analysis Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated b... | 12/14/2010 |
| 7818644 | Multi-stage test response compactors Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compac... | 10/19/2010 |
| 7814384 | Electrical diagnostic circuit and method for the testing and/or the diagnostic analysis of an integrated circuit An electrical diagnostic circuit and testing method is disclosed. In one embodiment, the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a ... | 10/12/2010 |
| 7805649 | Method and apparatus for selectively compacting test responses A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to t... | 09/28/2010 |
| 7788562 | Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data Pattern controllable LFSRs or MISRs are disclosed that are able to mask indeterminate states while performing tests on DUT outputs. At appropriate times, the MISRs or the LFSRs will mask the data being input to the MISRs or the LFSRs so that indeterminate states are... | 08/31/2010 |
| 7761761 | Semiconductor integrated circuit, test data generating device, LSI test device, and computer product A pattern correcting device corrects random test patterns generated by pseudo random number pattern generator (PRPG) into test patterns for a test to be input to shift registers. A pattern correcting device corrects the test patterns in unit of specified group, and ... | 07/20/2010 |
| 7743301 | Semiconductor integrated circuit and method of testing same A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-ov... | 06/22/2010 |
| 7681097 | Test system employing test controller compressing data, data compressing circuit and test method A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from... | 03/16/2010 |
| 7669100 | System and method for testing and providing an integrated circuit having multiple modules or submodules In an integrated circuit having a plurality of modules and/or submodules that each performs a substantially same function, defective modules and/or submodules are determined by creating a test signature from an input test pattern. The output of each module and/or su... | 02/23/2010 |
| 7653853 | Integrated circuit internal test circuit and method of testing by using test pattern and signature generations therewith A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test ... | 01/26/2010 |
| 7596736 | Iterative process for identifying systematics in data An iterative process for identifying systematics in data is provided. In general, a set of data is processed based on a signature definition to create a set of signature data. The set of signature data is then analyzed to identify common signatures. The set of signa... | 09/29/2009 |
| 7577888 | Self learning signatures A system and method for monitoring processes corresponding to measurable values based on signatures associated with the measurable values is provided. The signatures can be created based on data from auxiliary data sets or auxiliary data sources. Additional monitori... | 08/18/2009 |
| 7536619 | RAM testing apparatus and method Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be discriminated easily for the predetermined noted address or noted expected val... | 05/19/2009 |
| 7516381 | Integrated circuit test system A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor executes a predetermined program to perform expansion of a test pattern out... | 04/07/2009 |
| 7509550 | Fault diagnosis of compressed test responses Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is r... | 03/24/2009 |
| 7509551 | Direct logic diagnostics with signature-based fault dictionaries Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is recei... | 03/24/2009 |
| 7506234 | Signature circuit, semiconductor device having the same and method of reading signature information A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the sign... | 03/17/2009 |
| 7487420 | System and method for performing logic failure diagnosis using multiple input signature register output streams A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a space compaction system and, during testing, receives data values from... | 02/03/2009 |
| 7475311 | Systems and methods for diagnosing rate dependent errors using LBIST Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal oper... | 01/06/2009 |
| 7461311 | Device and method for creating a signature A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words and which serially shift the input data forward in a predefinable cy... | 12/02/2008 |
| 7461312 | Digital signature generation for hardware functional test A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to “tag”... | 12/02/2008 |
| 7441165 | Read-only memory and operational control method thereof A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data st... | 10/21/2008 |
| 7437638 | Boundary-Scan methods and apparatus Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to all of the drivers and hysteretic test receiver memories of a circuit... | 10/14/2008 |
| 7437641 | Systems and methods for signature circuits Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in ... | 10/14/2008 |
| 7437642 | Model train command protocol using front and back error bytes A model train command protocol using front and back error bytes is disclosed. The front error byte is used to encode the data so that it is securely transmitted. The back error byte checks for proper transmission of the data itself. The entire encoded data sequence ... | 10/14/2008 |
