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| Number | Title | Issue Date |
| 8185790 | Resynchronization memory in series/parallel with control/output data scan cells An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data ... | 05/22/2012 |
| 8145963 | Semiconductor integrated circuit device and delay fault testing method thereof A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a ... | 03/27/2012 |
| 8145964 | Scan test circuit and scan test control method A circuit includes a control flip-flop inputting a scan control signal and a scan path chain formed of scan storage elements serially connected. The scan path chain performs a shift operation as a first mode when the control flip-flop outputs a first status value, a... | 03/27/2012 |
| 8140925 | Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises... | 03/20/2012 |
| 8127189 | Gates and sync circuitry connecting TAP to serial communications circuitry The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal... | 02/28/2012 |
| 8127188 | Semiconductor integrated circuit and design automation system A scan chain circuit causes a plurality of flip-flops to function as shift registers during execution of a scan test and can execute a scan shift that serially transfers test pattern data for the scan test. A clock gating circuit controls output of a pulse of a cloc... | 02/28/2012 |
| 8122311 | Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner u... | 02/21/2012 |
| 8117511 | Communication device and method of correcting the same A communication device includes a reference clock generator that generates a first reference clock signal, and a super frame timer that clocks a period of super frame based on the first reference clock signal generated by the reference clock generator. The communica... | 02/14/2012 |
| 8091002 | Multiple-capture DFT system to reduce peak capture power during self-test or scan test A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clo... | 01/03/2012 |
| 8086924 | Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple syste... | 12/27/2011 |
| 8074133 | Method and apparatus for testing delay faults An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock i... | 12/06/2011 |
| 8073855 | Communication control device and communication control system The present invention provides a technique for enabling a high-speed communication control apparatus. A packet processing circuit of a communication control apparatus includes a user database, a virus list, a whitelist, a blacklist and a common category list.... | 12/06/2011 |
| 8046651 | Compare circuit receiving scan register and inverted clock flip-flop data The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to p... | 10/25/2011 |
| 8042015 | High-speed semiconductor memory test device A semiconductor test device includes; a tester providing a first clock signal, first test data, a control signal and a first clock signal, a reference clock generating unit generating a reference clock signal, a clock converting unit receiving the reference clock si... | 10/18/2011 |
| 8037385 | Scan chain circuit and method A scan chain circuit is disclosed. The scan chain circuit includes a chain of serially coupled clocked circuits. In a first mode of operation, each of the clocked circuits toggles in response to a rising edge of a clock signal. In a second mode of operation, a first... | 10/11/2011 |
| 8028209 | Scalable scan system for system-on-chip design A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of... | 09/27/2011 |
| 8028210 | Semiconductor device An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the... | 09/27/2011 |
| 7987401 | System and method for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing Presented herein are system(s) and method(s) for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing. In one embodiment, there is presented a system for scan testing. The system comprises an ATE ... | 07/26/2011 |
| 7984351 | Data transfer device and method thereof A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock doma... | 07/19/2011 |
| 7984350 | Logic circuitry and recording medium Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to... | 07/19/2011 |
| 7975197 | On-chip scan clock generator for ASIC testing A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses ... | 07/05/2011 |
| 7971115 | Method and apparatus for detecting and correcting errors in a parallel to serial circuit A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth port... | 06/28/2011 |
| 7966537 | Digital reliability monitor having autonomic repair and notification capability A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configu... | 06/21/2011 |
| 7962819 | Test mode soft reset circuitry and methods An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan c... | 06/14/2011 |
| 7941720 | Scan test circuit and scan test control method A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a shift operation mode when an output of the control FF is a first status value, and in a norma... | 05/10/2011 |
| 7930608 | Circuit for controlling voltage fluctuation in integrated circuit An integrated circuit for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and latches synchronously operated in accordance with operating clock signals distributed via the clock buffers. The circuit comprises a mechanis... | 04/19/2011 |
| 7930609 | Apparatus and method for verifying target circuit A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first da... | 04/19/2011 |
| 7925946 | DDR gate and delay clock circuitry for parallel interface registers A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the ... | 04/12/2011 |
| 7917824 | Scan path adaptor with state machine, counter, and gate circuitry Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time o... | 03/29/2011 |
| 7917823 | Decoupled clocking in testing architecture and method of testing A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock... | 03/29/2011 |
| 7913139 | Semiconductor device An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the... | 03/22/2011 |
| 7913138 | Semiconductor integrated circuit A semiconductor integrated circuit, including a data input unit for receiving an input data signal to be supplied to an external data input terminal, a storage unit for storing the input data signal received by the data input unit, a timing generating unit for gener... | 03/22/2011 |
| 7908536 | Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across t... | 03/15/2011 |
| 7908537 | Boundary scan path method and system with functional and non-functional scan cell memories An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data ... | 03/15/2011 |
| 7900108 | Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clk1-clko) for at least some of the... | 03/01/2011 |
| 7890826 | Method and apparatus for test of asynchronous pipelines A method and apparatus for test of asynchronous pipelines. An asynchronous data pipeline includes first and second pluralities of pipeline stages in an alternating sequence. Each of the pipeline stages includes a control circuit, a latch circuit configured to latch ... | 02/15/2011 |
| 7882410 | Launch-on-shift support for on-chip-clocking A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains a... | 02/01/2011 |
| 7882411 | Shift register, data line driving circuit, scanning line driving circuit, electro-optical device, and electronic apparatus To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit spec... | 02/01/2011 |
| 7870452 | Scan testing methods A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement (20) timed with a first, scan, clock signal (42). The test vector b... | 01/11/2011 |
| 7861130 | System and method of determining the speed of digital application specific integrated circuits According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection... | 12/28/2010 |
