Class 714/730 - Addressing

Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter including data which specifies a location.
No. of patents: 97
Last issue date: 04/24/2012

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Number	Title	Issue Date
8166358	Test access port with address and command capability The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands fo...	04/24/2012
7484152	Securing the test mode of an integrated circuit An electronic circuit includes a logic circuit formed from a plurality of logic units. The electronic circuit also includes a plurality of memory units capable of forming a shift register, capable of being connected to the logic units, and having terminals for recep...	01/27/2009
7444577	Memory device testing to support address-differentiated refresh rates A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of stor...	10/28/2008
7444573	VLCT programmation/read protocol An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address spec...	10/28/2008
7437643	Automated BIST execution scheme for a link Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is p...	10/14/2008
7418636	Addressing error and address detection systems and methods Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether t...	08/26/2008
7403901	Error and load summary reporting in a health care solution environment A system, method and computer program are provided for generating error and summary reports for a data load. A plurality of records to be loaded in a database are received. The records may include medical records. A data management template corresponding to the reco...	07/22/2008
7383480	Scanning latches using selecting array A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. B...	06/03/2008
7356436	Method, system, and storage medium for estimating and improving test case generation A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to me...	04/08/2008
7315936	Enhanced boolean processor A set of processors, co-processors and processor cores having a Boolean logic unit, wherein the Boolean logic unit is operable, respectively, for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, Disjunctive Normal Fo...	01/01/2008
7281179	Memory device and input signal control method of a memory device A memory device and a method of controlling an input signal of the memory device. In the method of controlling an input signal according to test modes, it is determined whether the input signal is in a first test mode or a second test mode. If the memory device is i...	10/09/2007
7266745	Programmable scan shift speed control for LBIST Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. Th...	09/04/2007
7254691	Queuing and aligning data Queuing and ordering data is described. Data is stored or queued in concatenated memories where each of the memories has a respective set of data out ports. An aligner having multiplexers arranged in a lane sequence are coupled to each set of the data out ports. A v...	08/07/2007
7240260	Stimulus generation In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a re...	07/03/2007
7231563	Method and apparatus for high speed testing of latch based random access memory A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan cl...	06/12/2007
7219283	IC with TAP, STP and lock out controlled output buffer Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. A first buffer has an input connected to a scan output lead, a control input, and an ou...	05/15/2007
7206237	Apparatus and method for testing a memory device with multiple address generators An apparatus includes a test signal path to provide a test signal to a memory cell array responsive to an address generating command, the test signal to access a memory cell within the memory cell array, a failure address path to generate a failure address responsiv...	04/17/2007
7185249	Method and apparatus for secure scan testing A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from ...	02/27/2007
7165198	System for testing an integrated circuit using multiple test modes A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage device...	01/16/2007
7155647	Scan of chip state from a hierarchical design A method and mechanism for observation, testing, and diagnosis with scan chains. A device under test is configured to support scan chains. The device includes multiple blocks, each of which are configured to be individually tested with separate scan chains. Each blo...	12/26/2006
7089468	Program-controlled unit and method for identifying and/or analyzing errors in program-controlled units The program-controlled unit, during the execution of the program, can switch itself to a state in which selected elements that can be connected to form scan chains or all of the elements can no longer change their state, according to a predetermined result. If these...	08/08/2006
7080299	Resetting latch circuits within a functional circuit and a test wrapper circuit Within an integrated circuit 2 a functional block of circuitry 6 has an associated test wrapper circuit 10. The functional block of circuitry 6 includes functional latches 14 at least some of which may also serve as shared test lat...	07/18/2006
7069485	Reading data from a memory with a memory access controller A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and ...	06/27/2006
7036064	Synchronization point across different memory BIST controllers A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An ou...	04/25/2006
7035784	Data-driven method simulator and simulation process A simulator and/or simulation process operates by receiving a message from a system; comparing the received message to information stored in a response file used to simulate system response; and simulating a response to the system by outputting a response stored in ...	04/25/2006
7032141	Semiconductor device including test-facilitating circuit using built-in self test circuit A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory cor...	04/18/2006
7003707	IC tap/scan test port access with tap lock circuitry Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. This arrangement provides for the merged TAP and scan test port interfaces to be select...	02/21/2006
6998866	Circuit and method for monitoring defects A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sens...	02/14/2006
6992498	Test apparatus for testing integrated modules and method for operating a test apparatus A test apparatus for testing integrated modules has a plurality of connection locations on a carrier substrate. An integrated module may be connected, via a connection location, to a test unit connected to the carrier substrate. The connection locations are arranged...	01/31/2006
6971045	Reducing tester channels for high pinout integrated circuits An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input si...	11/29/2005
6963963	Multiprocessor system having a shared main memory accessible by all processor units A data processing (10) includes memory management circuitry (14) which allows additional control over the physical address (83) and over the address attributes (84) which are provided for use by data processing system (10). One use...	11/08/2005
6964002	Scan chain design using skewed clocks A scan chain comprising a series of flip-flops and two clock signals, where each clock signal is coupled to alternating flip-flops in the series. The second clock signal is typically 180 degrees out of phase with the first clock signal. The two clock signals may be ...	11/08/2005
6918057	Architecture, circuitry and method for controlling a subsystem through a JTAG access port Architecture, circuitry, and methods are provided for programming, writing to, or reading from one or more integrated circuits which may be arranged upon a printed circuit board. Programming and read/write operations can, therefore, be done after integrated circuits...	07/12/2005
6915453	Method for controlling starting operation of unit and executing self-checking test When a testing system is connected to a debug port of a tape drive unit or a SCSI bus, a self-checking test for a fabricating process is executed. When the testing system is not connected, the self-checking test for normal operation is executed. And in a test of a s...	07/05/2005
6912681	Circuit cell for test pattern generation and test pattern compression A circuit for test pattern generation compression of circuits with a built-in self-test function has a test data coupling circuit having a test data input for receiving a test data input signal from a circuit cell connected upstream, which signal can be stored in a ...	06/28/2005
6907557	System and method for testing a group of related products A system and method for testing a group of related products or devices. According to one embodiment, the user may first manually create a base test sequence, and child test sequences may then be created based on the base test sequence. The user may include various s...	06/14/2005
6865660	Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern e...	03/08/2005
6836440	Method of checking electrical connections between a memory module and a semiconductor memory chip Two methods check functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. Ruptured solder contacts ...	12/28/2004
6769084	Built-in self test circuit employing a linear feedback shift register A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated fro...	07/27/2004
6728915	IC with shared scan cells selectively connected in scan path This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in control scan cells are dedicated for test and not used functionally. The control scan cells can be scann...	04/27/2004

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Class 714/730 - Addressing