Class 714/729 - Plural scan paths

Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter having more than one group of shift register
No. of patents: 468
Last issue date: 05/29/2012

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Number	Title	Issue Date
8190954	Core circuit test architecture A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable si...	05/29/2012
8185789	Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay t...	05/22/2012
8112684	Input linking circuitry connected to test mode select and enables IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, ...	02/07/2012
8103926	Method and apparatus for synthesis of augmented multimode compactors Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described. ...	01/24/2012
8099642	Formatter selectively outputting scan stimulus data from scan response data The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a nov...	01/17/2012
8065578	Inverted TCK access port selector selecting one of plural TAPs The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal ter...	11/22/2011
8055964	Semiconductor device having plural clock domains which receive scan clock in common A semiconductor device, includes a plurality of scan chains for testing a plurality of clock domains whose operating frequencies are different from one another, each of the plurality of scan chains including a plurality of flip-flop circuits, a clock oscillator whic...	11/08/2011
8055965	Semiconductor integrated circuit and method of testing the same A semiconductor integrated circuit includes: a plurality of scan flip-flops configured to form a scan chain in a scan test; and a plurality of clock gating circuits connected between a clock input and corresponding portions of the plurality of scan flip-flops, respe...	11/08/2011
8051349	Link instruction register with instruction register, and gate and multiplexer A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the bo...	11/01/2011
8046650	TAP with control circuitry connected to device address port The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure...	10/25/2011
8024631	Scan testing system and method A scan test circuit includes a plurality of tester inputs that receive scan test data for performance of a scan test of a circuit under test. The scan test circuit also includes first and second sets of scan chains that include first and second sets of state variabl...	09/20/2011
8015466	Adapting scan-BIST architectures for low power operation A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-...	09/06/2011
8015465	Scan control method and device A scan control method of a circuit device including setting information indicating scan mode in a register is provided. The scan control method includes cutting an output of scan-out data to a test access port controller and an input of scan-in data from a data regi...	09/06/2011
8015464	Segmented scan paths with cache bit memory inputs Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay t...	09/06/2011
8006152	Scan chain fail diagnostics A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR a...	08/23/2011
8001433	Scan testing architectures for power-shutoff aware systems In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into cir...	08/16/2011
7996740	Adaptor With Clocks For Like Parts of Different Scan Paths Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time o...	08/09/2011
7979764	Distributed test compression for integrated circuits A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, se...	07/12/2011
7966536	Method and apparatus for automatic scan completion in the event of a system checkstop A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connecte...	06/21/2011
7962818	Reduced signaling interface method and apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be...	06/14/2011
7954027	Reduced signaling interface method and apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be...	05/31/2011
7954026	TAM controller connected with TAM and functional core wrapper circuit A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. T...	05/31/2011
7949921	Method and apparatus for synthesis of augmented multimode compactors Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described. An integrated circuit has circuitry that compacts test response data from scan chains in the integrated circuit under test. In many cases groups of the scan ...	05/24/2011
7949920	DFT techniques to reduce test time and power for SoCs A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound...	05/24/2011
7945834	IC testing methods and apparatus A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0] . . . wpi[N−1]) and respective parallel outputs (wpo[0] . . . wpo[N−1]). The scan chain segments comprise a bank (62) of cells ...	05/17/2011
7945833	Method and apparatus for pipelined scan compression A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit...	05/17/2011
7941719	IC testing methods and apparatus A shift register circuit is provided for storing instruction data for the testing of an integrated circuit core. The shift register circuit comprises a plurality of stages, each stage comprising a serial input (si) and a serial output (so) and a parallel output (wir...	05/10/2011
7930607	Circuit for boosting encoding capabilities of test stimulus decompressors The circuit for boosting encoding capabilities of test stimulus decompressors is utilized in conjunction with a stimulus decompressor. The circuit, called align-encode is inserted between the decompressor and internal. The scan chains feed into a response compactor....	04/19/2011
7925944	Semiconductor device In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A...	04/12/2011
7925945	Generator/compactor scan circuit low power adapter A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-...	04/12/2011
7917821	System-on-chip performing multi-phase scan chain and method thereof A system on chip (SOC) may include function blocks, and a scan chain in each of the function blocks, the scan chains being adapted to conduct scan test operations in sync with a respective one of a plurality of clock signals having a different phase relative to each...	03/29/2011
7917822	Serial I/O using JTAG TCK and TMS signals The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal...	03/29/2011
7913137	On-chip comparison and response collection tools and techniques Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compac...	03/22/2011
7908535	Scan testable register file Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage b...	03/15/2011
7908534	Diagnosable general purpose test registers scan chain design A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) ...	03/15/2011
7904774	Wafer scale testing using a 2 signal JTAG interface Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG...	03/08/2011
7904773	Multiple-capture DFT system for scan-based integrated circuits A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain h...	03/08/2011
7900107	High speed ATPG testing circuit and method The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives...	03/01/2011
7895489	Matrix system and method for debugging scan structure An aspect of the present invention is drawn to a system that includes an automatic test engine, a decompressor, a first scan chain, a second scan chain, a compactor and a debug output. The automatic test engine is operable to output a test output, to receive a resul...	02/22/2011
7882409	Method and apparatus for synthesis of augmented multimode compactors Proposed are methods and apparatuses for synthesis of a new class of compressors called augmented multimode compactors, capable of achieving a flexible trade-off between compaction ratio, observability, control data volume and diagnostic properties in the presence o...	02/01/2011

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Class 714/729 - Plural scan paths