Famous Patents
British merchant Peter Durand invented the tin can in 1810.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8037384 | Semiconductor device A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provi... | 10/11/2011 |
| 7979763 | Fully X-tolerant, very high scan compression scan test systems and techniques Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression... | 07/12/2011 |
| 7941718 | Electronic device testing system A method and system for testing an electronic device is disclosed. The method includes loading a first test into a test pattern generator of a first device and generating a first test pattern at the test pattern generator. A second test seed is loaded into the test ... | 05/10/2011 |
| 7913136 | Method for performing a logic built-in-self-test in an electronic circuit The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10... | 03/22/2011 |
| 7895488 | Control of clock gate cells during scan testing A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently con... | 02/22/2011 |
| 7865792 | Test generation methods for reducing power dissipation and supply currents Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In ... | 01/04/2011 |
| 7840865 | Built-in self-test of integrated circuits using selectable weighting of test patterns A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing th... | 11/23/2010 |
| 7788560 | Interleaver with linear feedback shift register An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The inter... | 08/31/2010 |
| 7752515 | Accelerated scan circuitry and method for reducing scan test data volume and execution time An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired C... | 07/06/2010 |
| 7707471 | Method of defining fault pattern of equipment and method of monitoring equipment using the same Provided is a method of forming reference information for defining a fault pattern of equipment, and monitoring equipment. One example embodiment method may include performing an angle spectrum analysis by re-classifying fault points distributed on a plane, the plan... | 04/27/2010 |
| RE41187 | Variable clocked scan test circuitry and method A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift c... | 03/30/2010 |
| 7673204 | Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available... | 03/02/2010 |
| 7506232 | Decompressor/PRPG for applying pseudo-random and deterministic test patterns A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decom... | 03/17/2009 |
| 7484151 | Method and apparatus for testing logic circuit designs Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan input... | 01/27/2009 |
| 7444558 | Programmable measurement mode for a serial point to point link A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and ... | 10/28/2008 |
| 7437531 | Testing memories Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo r... | 10/14/2008 |
| 7426666 | Noisy channel emulator for high speed data Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is ... | 09/16/2008 |
| 7424417 | System and method for clock domain grouping using data path relationships A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of ea... | 09/09/2008 |
| 7421629 | Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to co... | 09/02/2008 |
| 7415649 | Semi-conductor component test device with shift register, and semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-condu... | 08/19/2008 |
| 7409324 | Design support system The design support system regarding the present invention comprises a node data storage means that stores node data to generate functional models which present a group of function nodes which are functions divided from performance function of apparatus which is an o... | 08/05/2008 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 7404127 | Circuitry with multiplexed dedicated and shared scan path cells An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data ... | 07/22/2008 |
| 7386777 | Systems and methods for processing automatically generated test patterns Representative embodiments are generally directed to storing compressed test pattern data on an automated test equipment (ATE) device. In one embodiment, the test pattern data is compressed according to a linear feedback shift register (LFSR). The LFSR may possess a... | 06/10/2008 |
| 7355467 | Physical layers Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit bra... | 04/08/2008 |
| 7356436 | Method, system, and storage medium for estimating and improving test case generation A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to me... | 04/08/2008 |
| 7353470 | Variable clocked scan test improvements Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for s... | 04/01/2008 |
| 7346817 | Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first ... | 03/18/2008 |
| 7336275 | Pseudo random number generator and method A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermedi... | 02/26/2008 |
| 7334172 | Transition fault detection register with extended shift mode An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a cloc... | 02/19/2008 |
| 7319320 | Rotation angle detecting device An improved rotation angle detecting device that detects a rotation angle of a first member relative to a second member is proposed. The rotation angle detecting device includes a magnet unit fixed to the first member and a pair of magnetic sensors fixed to the seco... | 01/15/2008 |
| 7320114 | Method and system for verification of soft error handling with application to CMT processors A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in ... | 01/15/2008 |
| 7317776 | Efficient pseudo-noise sequence generation for spread spectrum applications The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise generators. A first embodiment of this invention includes a plurality... | 01/08/2008 |
| 7313738 | System and method for system-on-chip interconnect verification A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip componen... | 12/25/2007 |
| 7308607 | Periodic checkpointing in a redundantly multi-threaded architecture A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the c... | 12/11/2007 |
| 7302656 | Method and system for performing functional verification of logic circuits A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form t... | 11/27/2007 |
| 7302626 | Test pattern compression with pattern-independent design-independent seed compression The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set. ... | 11/27/2007 |
| 7298779 | Fast code acquisition method based on signed-rank statistic The present invention relates to the fast code acquisition methods based on signed-rank statistic. In more detail, it presents novel detectors required for PN (PN) code acquisition in DS/SS system. In accordance with the present invention, first, the LOR (LOR... | 11/20/2007 |
| 7296202 | Semiconductor module with a configuration for the self-test of a plurality of interface circuits and test method A semiconductor module with a plurality of interface circuits has a configuration for the self-test of interface circuits, with two equally sized groups of interface circuits such that each interface circuit of the first group is assigned exactly one interface circu... | 11/13/2007 |
| 7263675 | Tuple propagator and its use in analysis of mixed clock domain designs Names of signals are propagated through a circuit design inside tuples, with each tuple including at least a signal name and a sequential depth. A tuple being propagated is added to a list of zero or more tuples currently identified with a circuit element, unless a ... | 08/28/2007 |
