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| Number | Title | Issue Date |
| 8112683 | System and application debugging Systems, apparatuses, and methods for system and application debugging are described herein. A tested platform may include a debug event monitor in a boundary scan interface that detects a debug event in a process and determines a characteristic associated with the ... | 02/07/2012 |
| 8108742 | Tap control of TCA scan clock and scan enable The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to ... | 01/31/2012 |
| 8095840 | Serial scan chain in a star configuration A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configura... | 01/10/2012 |
| 8078926 | Test pin gating for dynamic optimization An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the int... | 12/13/2011 |
| 8078927 | Wrapper leads gating TAP instruction and data registers In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment... | 12/13/2011 |
| 8065577 | Dual controllers for scan paths, distributors, and collectors Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consum... | 11/22/2011 |
| 8055963 | Accessing sequential data in a microcontroller System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies a... | 11/08/2011 |
| 8046649 | Scan circuits formed peripheral of core circuits with control leads An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP le... | 10/25/2011 |
| 8032806 | Input-output device testing including initializing and leakage testing input-output devices Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, ... | 10/04/2011 |
| 8032807 | Scan control method, scan control circuit and apparatus A scan control method for a circuit device connected with a first bus and having a test access port controller, including setting information indicating a register to be scanned in the circuit device, a number of scan shifts and a scan start via a second bus differe... | 10/04/2011 |
| 8024630 | Debugging module for electronic device and method thereof A debugging module for connecting an IC to a JTAG debugger device includes a JTAG interface, an earphone circuit, a USB interface, a switching unit, and a reset circuit. The earphone circuit is electrically connected to the JTAG interface via the switching unit. The... | 09/20/2011 |
| 8020058 | Multi-chip digital system having a plurality of controllers with self-identifying signal The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality ... | 09/13/2011 |
| 8015462 | Test circuit A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an inte... | 09/06/2011 |
| 8015463 | IC with TAP, DIO interface, SIPE, and PISO circuits Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG... | 09/06/2011 |
| 8006151 | TAP and shadow port operating on rising and falling TCK The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port ... | 08/23/2011 |
| 7996739 | Avoiding race conditions at clock domain crossings in an edge based scan design A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the ... | 08/09/2011 |
| 7992065 | Automatic scan format selection based on scan topology selection A method for specifying a signaling protocol to be used by a controller in a group of controllers connected with shared signaling is provided in which the controller is selected based on selection criteria received by the controller and the signaling protocol is spe... | 08/02/2011 |
| 7992064 | Selecting a scan topology A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection event and a selection sequence containing selection criteria from a signal line at each of the controllers, ... | 08/02/2011 |
| 7984347 | System and method for sharing a communications link between multiple communications protocols A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protoc... | 07/19/2011 |
| 7984348 | Series equivalent scans across multiple scan topologies Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and perfo... | 07/19/2011 |
| 7984349 | IC multiplexer control circuitry for tap selection circuitry Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap ... | 07/19/2011 |
| 7979762 | Integrated circuit board with JTAG functions In an integrated circuit board, a plurality of integrated circuits to be checked are connected together in a star shape. Operation clock data for JTAG of each integrated circuit and check data for checking each integrated circuit are stored. When an integrated circu... | 07/12/2011 |
| 7975196 | Resynchronization memory in series/parallel with control/data scan cells An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data ... | 07/05/2011 |
| 7975195 | Scan architecture for full custom blocks with improved scan latch A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by ... | 07/05/2011 |
| 7966535 | Secure scan design A circuit configuration for testing integrated circuitry featuring a number of system scan flip flops wired in series and connected to the integrated circuitry for inputting test signals and receiving test data back. At the front and back ends of the system scan fli... | 06/21/2011 |
| 7962814 | Mode selection based on special sequence of state machine states A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermin... | 06/14/2011 |
| 7962816 | I/O switches and serializer for each parallel scan register An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the... | 06/14/2011 |
| 7962817 | IEEE 1149.1 and P1500 test interfaces combined circuits and processes In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP b... | 06/14/2011 |
| 7962815 | Tap demultiplexer with select and select one outputs for HTML An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hie... | 06/14/2011 |
| 7962813 | 1149.1 tap linking modules IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, ... | 06/14/2011 |
| 7958419 | Entering a shift-DR state in one of star connected components A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configura... | 06/07/2011 |
| 7958420 | Clock delay circuits and multiplexer connected to boundary scan circuitry A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producin... | 06/07/2011 |
| 7949917 | Maintaining data coherency in multi-clock systems A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock ... | 05/24/2011 |
| 7949919 | Microelectronic device and pin arrangement method thereof The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test s... | 05/24/2011 |
| 7949918 | Asynchronous communication using standard boundary architecture cells An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core pr... | 05/24/2011 |
| 7945832 | Interface to full and reduced pin JTAG devices The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The acce... | 05/17/2011 |
| 7945831 | Gating TDO from plural JTAG circuits Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary sca... | 05/17/2011 |
| 7941717 | IC testing methods and apparatus A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is ... | 05/10/2011 |
| 7937635 | Selectively accessing test access ports in a multiple test access port environment A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ... | 05/03/2011 |
| 7930606 | Selectively debugging processor cores through instruction codes A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m≧2) and less than the total number of m bits a... | 04/19/2011 |
