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| Number | Title | Issue Date |
| 8438438 | Enhanced diagnosis with limited failure cycles Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which ... | 05/07/2013 |
| 8438436 | Secure design-for-test scan chains A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling ... | 05/07/2013 |
| 8438437 | Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan chains (101.k, ... | 05/07/2013 |
| 8438439 | Integrated circuit having a scan chain and testing method for a chip An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which ... | 05/07/2013 |
| 8429472 | Generating device, generating method, and program Provided are a generation device to reduce launch switching activity, yield loss risk, and power consumption of testing, even in the at-speed scan testing, even with a small number of don't-care (X) bits in input bits as in test compression, without any impact on te... | 04/23/2013 |
| 8429471 | Microprocessor apparatus and method for securing a programmable fuse array An apparatus for precluding the use of extended JTAG operations, including a JTAG control chain, a feature fuse, a level sensor, an access controller, and a blow controller. The JTAG control chain enables/disables the extended JTAG operations. The feature fuse indic... | 04/23/2013 |
| 8423844 | Dense register array for enabling scan out observation of both L1 and L2 latches A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first... | 04/16/2013 |
| 8423843 | Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test Scan blocks with scan chains are used to partition and test semiconductor devices using scan groups. The partitioning of the semiconductor device enables testing of all elements within each scan block, at speed, to provide fault coverage. A challenge in scan testing... | 04/16/2013 |
| 8412991 | Scan chain fault diagnosis Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. A method for identifying a reference scan cell is provided, the method including, ... | 04/02/2013 |
| 8407540 | Low overhead circuit and method for predicting timing errors A data processing circuitry includes a data input, a data output and a processing path arranged between the data input and the data output. The circuitry includes a plurality of retention circuits arranged in parallel with the processing path. At least one potential... | 03/26/2013 |
| 8407539 | Semiconductor device test circuit, semiconductor device, and its manufacturing method The test circuit can apply a stress to each node of each object combinational circuit in the semiconductor device and suppress the semiconductor circuit overhead when in burn-in or leak test operations for the semiconductor device while it has been impossible to app... | 03/26/2013 |
| 8407541 | Dynamic test signal routing controller Integrated circuits with dynamic pin routing capabilities are provided. An integrated circuit may include circuitry under test and a dynamic signal routing controller. The dynamic signal routing controller may include multiplexers, a test register, and a signal sele... | 03/26/2013 |
| 8402328 | Apparatus and method for protecting soft errors An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance opera... | 03/19/2013 |
| 8402329 | Scan test circuit, and method and program for designing same Flip-flops 201 to 206 constitute a scan path shift register. During shift mode operation, a clock signal CLK is supplied to clock terminals of the flip-flops 201, 203, and 205, a signal obtained by having an inverted clock control circuit... | 03/19/2013 |
| 8397112 | Test chain testability in a system for testing tri-state functionality An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing th... | 03/12/2013 |
| 8392773 | Bi-directional TMS lead carrying TMS and frame data in/out signals The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an ... | 03/05/2013 |
| 8386863 | Scanning-capable latch device, scan chain device, and scanning method with latch circuits In a scanning-capable latch circuit, main latch circuits respectively corresponding to data inputs D1 to D4 are connected in series and, except the last-stage main latch circuit, the scanning output from each main latch circuit becomes the scanning inp... | 02/26/2013 |
| 8365029 | Digital circuits and methods for testing a digital circuit Digital circuits and methods for testing a digital circuit are disclosed. One embodiment provides a digital circuit having a first plurality of storage elements, and a second plurality of storage elements. The digital circuit is operable in a first operation mode an... | 01/29/2013 |
| 8359502 | TDI multiplexer gating controlled by override selection logic A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain... | 01/22/2013 |
| 8356218 | Fault location estimation device, fault location estimation method, and program A fault location estimation device includes: a faulty scan chain identification unit that identifies a faulty scan chain and its fault type based on result of operation verification test; a faulty scan FF narrowing unit that compares test result of the faulty scan c... | 01/15/2013 |
| 8356217 | Storage circuit, integrated circuit, and scanning method A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit ... | 01/15/2013 |
| 8352815 | Circuit and method operable in functional and diagnostic modes The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a ... | 01/08/2013 |
| 8352816 | Adapter leads connected to test circuitry and third leads set A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select regist... | 01/08/2013 |
| 8341472 | Apparatus and method for tamper protection of a microprocessor fuse array An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG opera... | 12/25/2012 |
| 8341473 | Microprocessor and method for detecting faults therein A microprocessor has a silicon area comprising a plurality of transistors implemented on the silicon area and a fault detection circuit occupying less than 20% of the silicon area and configured to detect faults at runtime in at least 80% of the plurality of transis... | 12/25/2012 |
| 8341474 | Moving all TAP controllers through update-IR state after selecting individual TAPs A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configura... | 12/25/2012 |
| 8335952 | Tap and scan test port with IR lock out output Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection ... | 12/18/2012 |
| 8332698 | Scan latch with phase-free scan enable A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period w... | 12/11/2012 |
| 8327203 | State machine transitioning from sequence 1 to sequence 2 to idle 2 A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alter... | 12/04/2012 |
| 8324917 | Logic applying serial test bits to scan paths in parallel An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional cir... | 12/04/2012 |
| 8327202 | System and method for scan testing A scan system comprises a scan engine adapted to receive a scan request from a host system for performing a scan test on a system-under-test. The scan engine comprises dedicated logic where a state of the dedicated logic is adapted to control processing of the scan ... | 12/04/2012 |
| 8316265 | Test pattern generation for diagnosing scan chain failures Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns... | 11/20/2012 |
| 8301943 | Pulse flop with enhanced scan implementation In an embodiment, a clocked storage device such as a pulse flop is provided. The pulse flop includes a latch coupled to receive a scan data input to the pulse flop. The latch receives the scan data input during one of the phases of the clock, and retains the receive... | 10/30/2012 |
| 8286040 | Device and method for testing a circuit A device having testing capabilities, the device includes: a tested circuit that includes multiple scan chains; a compactor adapted to compress scan chain test responses; a mask unit, connected between the multiple scan chains and the compactor, wherein the mask uni... | 10/09/2012 |
| 8286041 | Semiconductor integrated circuit and method of saving and restoring internal state of the same A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in... | 10/09/2012 |
| 8281194 | Scan path switch testing of output buffer with ESD The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die. ... | 10/02/2012 |
| 8281195 | Scan architecture for full custom blocks An output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/... | 10/02/2012 |
| 8281279 | Creating scan chain definition from high-level model using high-level model simulation Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into c... | 10/02/2012 |
| 8276030 | Scan distributor and parallel scan paths with controlled output buffer Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan... | 09/25/2012 |
| 8261143 | Select signal and component override signal controlling multiplexing TDI/TDO A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain... | 09/04/2012 |
