Class 714/726 - Scan path testing (e.g., level sensitive scan design (LSSD))

Subclass of Class 714 - Error detection/correction and fault detection/recovery
Definition: Subject matter in which digital logic is designed for
No. of patents: 1579
Last issue date: 05/29/2012

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Number	Title	Issue Date
8190953	Method and system for selecting test vectors in statistical volume diagnosis using failed test data A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated...	05/29/2012
8185788	Semiconductor device test system with test interface means A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test stand...	05/22/2012
8181073	SRAM macro test flop A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a mast...	05/15/2012
8171357	Generating test sets for diagnosing scan chain failures Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnos...	05/01/2012
8166357	Implementing logic security feature for disabling integrated circuit test ports ability to scanout data A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal s...	04/24/2012
8150821	System and method for using generic utilities to perform database utilities on mainframe operated DB2 databases A system and method for performing database utilities on a DB2 database may include using a single procedure (proc) for each database utility function. At least one parameter may be provided, where the at least one parameter identifies a DB2 database name. A generic...	04/03/2012
8151152	Latch circuit including data input terminal and scan data input terminal, and semiconductor device and control method A latch circuit includes a first latch that stores data provided from a data input terminal when a clock is provided from a clock input terminal, and stores scan data provided from a scan data input terminal when a first scan clock is provided from a first scan cloc...	04/03/2012
8151153	Scan architecture for full custom blocks A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/s...	04/03/2012
8140923	Test circuit and method for testing of infant mortality related defects The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a ...	03/20/2012
8136003	JTAG debug test system adapter with three sets of leads A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select regist...	03/13/2012
8127186	Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the l...	02/28/2012
8127187	Method and apparatus of ATE IC scan test using FPGA-based system An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, tes...	02/28/2012
8122310	Input buffer, test switches and switch control with serial I/O The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die. ...	02/21/2012
8103924	Test access mechanism for multi-core processor or other integrated circuit A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined T...	01/24/2012
8103925	On-chip logic to support compressed X-masking for BIST Techniques are provided for X-masking using at least some masking information provided by on-chip logic, in lieu of masking information provided from off of the integrated circuit being tested. The masking information is provided by a masking information source on t...	01/24/2012
8099641	Multiplexer selecting STP clock signal with tap control outputs Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection ...	01/17/2012
8095838	Transitioning through idle 1, 2 and sequence 1 machine states A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alter...	01/10/2012
8095839	Position independent testing of circuits Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan...	01/10/2012
8095837	Method and apparatus for improving random pattern testing of logic structures A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves i...	01/10/2012
8086923	Accurately identifying failing scan bits in compression environments X-masking registers are added in front of a compactor in test data compression environment to remove unknown values. The X-masking registers block out some chains due to unknown values and select other chains to feed the compactor. This X-masking capability is used ...	12/27/2011
8078925	Apparatus for scan testing of integrated circuits with scan registers In one embodiment of the invention, an apparatus for scan testing an integrated circuit is provided. The apparatus includes a combinational logic network; and a device for reducing gate switching in the combinational logic network to reduce power consumption during ...	12/13/2011
8074132	Protecting data on integrated circuit Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a tri...	12/06/2011
8065575	Implementing isolation of VLSI scan chain using ABIST test patterns A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array...	11/22/2011
8065576	Test access port A semiconductor chip is described having a plurality of processing cores. The semiconductor chip also includes a plurality of test controllers. Each test controller is associated with a different one of the processing cores. The semiconductor chip also includes a te...	11/22/2011
8055961	Semiconductor device testing A semiconductor device test circuit includes a data producing unit to produce first test data to be fed into a semiconductor device, and expected value data; a first data retaining unit to retain the first test data, and feed the first test data into the semiconduct...	11/08/2011
8055962	Testing IC functional and test circuitry having separate input/output pads Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and powe...	11/08/2011
8051348	Integrated circuit testing using segmented scan chains An integrated circuit includes logic circuits including the first and second logic circuits, and a scan chain configured to test the logic circuits. The scan chain includes the first scan chain portion for testing the first logic circuit based on an input test patte...	11/01/2011
8051347	Scan-enabled method and system for testing a system-on-chip Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also...	11/01/2011
8046648	Method and apparatus for controlling operating modes of an electronic device A method and apparatus allows controlling a plurality of test operations in an electronic device, and in particular a volatile or non-volatile memory device in which a test mode has already been established, without the need for additional device connections. One su...	10/25/2011
8037382	Multi-mode programmable scan flop A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupl...	10/11/2011
8037383	Gating circuitry coupling selected scan paths between I/O scan bus A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable si...	10/11/2011
8020057	Comparator circuitry connected to input and output of tristate buffer A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on ...	09/13/2011
8018241	Logic applying different bit positions to respective scan paths An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional cir...	09/13/2011
8015461	Decompressors for low power decompression of test patterns Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a vari...	09/06/2011
8010857	Input/output boundary cells and output data summing scan cell Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit	08/30/2011
8010856	Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The...	08/30/2011
8006150	Circuit and method for increasing scan cell observability of response compactors The circuit and method for increasing the scan cell observability of response compactors is based on manipulation of x distribution in responses prior to taking them through a compactor. An x-align block is capable of delaying scan chains by judiciously computed val...	08/23/2011
8004298	IC with first and second distributors collectors and scan paths An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional cir...	08/23/2011
8006149	System and method for device performance characterization in physical and logical domains with AC SCAN testing A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The me...	08/23/2011
7996738	Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subd...	08/09/2011

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Class 714/726 - Scan path testing (e.g., level sensitive scan design (LSSD))