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| Number | Title | Issue Date |
| 8091001 | FPGA programming structure for ATPG test coverage Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a me... | 01/03/2012 |
| 8086922 | Programmable logic device with differential communications support Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a p... | 12/27/2011 |
| 8065574 | Soft error detection logic testing systems and methods A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresp... | 11/22/2011 |
| 8020131 | Method and apparatus for mapping flip-flop logic onto shift register logic Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design i... | 09/13/2011 |
| 8001511 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second ... | 08/16/2011 |
| 7996737 | Fingerprinted circuits and methods of making and identifying the same A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to i... | 08/09/2011 |
| 7987398 | Reconfigurable device Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration ... | 07/26/2011 |
| 7966534 | Identifying bitstream load issues in an integrated circuit A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the... | 06/21/2011 |
| 7958416 | Programmable logic device with differential communications support Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a p... | 06/07/2011 |
| RE42264 | Field programmable device A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circui... | 03/29/2011 |
| 7831873 | Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency diffe... | 11/09/2010 |
| 7831874 | Local defect memories on semiconductor substrates in a stack computer A reconfigurable high performance computer includes a stack of semiconductor substrate assemblies (SSAs). Some SSAs involve FPGA dice that are surface mounted, as bare dice, to a semiconductor substrate. Other SSAs involve memory dice that are surface mounted to a s... | 11/09/2010 |
| 7779318 | Self test structure for interconnect and logic element testing in programmable devices A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure... | 08/17/2010 |
| 7752511 | Devices, systems, and methods regarding a PLC system fault A method for providing a signal indicative of a set single bit flag, which is set for a scan cycle responsive to a detection of a fault in an Input/Output (I/O) device of a programmable logic controller (PLC) system or an I/O interface of the PLC system. Numerous ot... | 07/06/2010 |
| 7743296 | Logic analyzer systems and methods for programmable logic devices A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based ... | 06/22/2010 |
| 7739565 | Detecting corruption of configuration data of a programmable logic device A programmable logic device includes a configuration memory, a checker, and a redundant-logic detector. An array of programmable logic and interconnect resources is configurable to implement a selected user design. The configuration memory stores configuration data ... | 06/15/2010 |
| 7739564 | Testing an integrated circuit using dedicated function pins Testing an integrated circuit using dedicated function pins in a non-dedicated function test mode is described. In a first mode, a circuit block is activated for processing first information provided via dedicated function pins. In a second mode, the circuit block i... | 06/15/2010 |
| 7725787 | Testing of a programmable device A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element... | 05/25/2010 |
| 7712000 | ATE architecture and method for DFT oriented testing An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK ... | 05/04/2010 |
| 7702978 | Soft error location and sensitivity detection for programmable devices Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides... | 04/20/2010 |
| 7685485 | Functional failure analysis techniques for programmable integrated circuits Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysi... | 03/23/2010 |
| 7685486 | Testing of an embedded multiplexer having a plurality of inputs Functional testing of an integrated circuit (IC) is a part from a more comprehensive and thorough testing. An IC including an embedded select circuit module coupled to receive numerous input signals. The IC may also include control circuit coupled to receive input c... | 03/23/2010 |
| 7673201 | Recovering a prior state of a circuit design within a programmable integrated circuit A method of restoring a selected operational state of a circuit design implemented within a programmable integrated circuit (IC) can include pipelining a clock gating signal that selectively pauses a clock of the circuit design, and storing configuration data specif... | 03/02/2010 |
| 7669097 | Configurable IC with error detection and correction circuitry A configurable integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data, an error detection circuitry for detecting an error and a circuit that outputs from the IC an... | 02/23/2010 |
| 7647537 | Programmable logic device, information processing device and programmable logic device control method The present invention provides a programmable logic device including a main circuit unit capable of variably building desired user logic, based on configuration data inputted from a storage device, and a configuration data monitor unit for monitoring configuration d... | 01/12/2010 |
| 7644327 | System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented... | 01/05/2010 |
| 7620863 | Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utiliz... | 11/17/2009 |
| 7620862 | Method of and system for testing an integrated circuit The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated cir... | 11/17/2009 |
| 7603599 | Method to test routed networks Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from ... | 10/13/2009 |
| 7590904 | Systems and methods for detecting a failure event in a field programmable gate array An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in t... | 09/15/2009 |
| 7590903 | Re-configurable architecture for automated test equipment An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications... | 09/15/2009 |
| 7568136 | Reconfigurable system and method with corruption detection and recovery Reconfigurable circuits and systems having a recovery module coupled to the reconfigurable circuit and configured to access the configuration memory to retrieve configuration data stored in the configuration memory. The recovery module analyzes the retrieved configu... | 07/28/2009 |
| 7568137 | Method and apparatus for a clock and data recovery circuit A method and apparatus for a clock and data recovery circuit that includes a set of serializer/deserializer (SERDES) circuits that are adapted to sample progressively delayed versions of an input data stream. The sampling rate is slightly higher than the data rate o... | 07/28/2009 |
| 7546499 | Communication signal testing with a programmable logic device Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from ... | 06/09/2009 |
| 7539914 | Method of refreshing configuration data in an integrated circuit Configuration memory cells in an integrated circuit (IC) may be corrupted by cosmic radiation and other sources, causing improper operation of the IC. Reliability of an IC is improved by refreshing subsets, such as frames, of the configuration data according to a sc... | 05/26/2009 |
| 7536615 | Logic analyzer systems and methods for programmable logic devices A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the lo... | 05/19/2009 |
| 7529992 | Configurable integrated circuit with error correcting circuitry An integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data and error correction data, and error correction circuitry for receiving the configuration data, correcting... | 05/05/2009 |
| 7529993 | Method of selectively programming integrated circuits to compensate for process variations and/or mask revisions Methods of compensating for process variations and/or mask revisions in a programmable integrated circuit (IC). A non-volatile memory in the IC stores a value representing a process corner and/or mask revision for the IC. A configuration control circuit monitors a c... | 05/05/2009 |
| 7526694 | Integrated circuit internal test circuit and method of testing therewith A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test ... | 04/28/2009 |
| 7512849 | Reconfigurable programmable logic system with configuration recovery mode A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application ... | 03/31/2009 |
