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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7949912 | System and method of securing data stored in a memory A system and method of securing data stored in a memory are disclosed. The method comprises storing a payload data in a memory in one of first and second states related by a transform, reading the payload data from the memory, attempting to use the payload data for ... | 05/24/2011 |
| 7673196 | Methods and apparatus for communicating with a target circuit A system and method are disclosed which may include establishing a stored test vector, including a plurality of data bits, within a vector data engine; transmitting the stored test vector to a memory array; performing at least one arithmetic or logical operation upo... | 03/02/2010 |
| 7558993 | Test apparatus for semiconductor memory device A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output pattern to an expected output pattern using a plurality of comparators to... | 07/07/2009 |
| 7386769 | On chip diagnosis block with mixed redundancy On chip diagnosis method and on chip diagnosis block with mixed redundancy (IO redundancy and word-register redundancy) is provided. During a BIST (Built-In Self Test), information needed to apply redundancy resources is stored inside two arrays (fill_array, shift_a... | 06/10/2008 |
| 7366597 | Validating control system software variables A vehicle having a system for validating a variable signal for input to a processor-performed function. An input module receives the signal. A processor tests first and second storage locations of a memory. After testing, the processor stores the signal in the first... | 04/29/2008 |
| 7360118 | Method and system for verifying data in a shadow memory A system for verifying data in a shadow memory is provided that includes a main memory, a shadow memory, a shadow memory initializer, and a shadow memory verifier. The main memory is operable to store main data persistently. The shadow memory is operable to store sh... | 04/15/2008 |
| 7353400 | Secure program execution depending on predictable error correction A CPU is provided with an ability to modify its operation, with respect to error correction, as a programmable feature. An error correction scheme is selected to be performed by the error correcting circuit. The compiled program may have intentionally introduced err... | 04/01/2008 |
| 7340665 | Shared redundancy in error correcting code A method and apparatus are provided for storing data. The method and apparatus generate a plurality of ECC codewords, which define a cooperative block. Each ECC codeword includes a plurality of information symbols and first and second sets of corresponding redundanc... | 03/04/2008 |
| 7296197 | Metadata-facilitated software testing Described herein are one or more implementations for facilitation of computer software testing. One or more implementations, described herein, determine logical type of one or more test input-parameters based upon metadata placed on a function under test (FUT) of so... | 11/13/2007 |
| 7287204 | Memory unit test The invention relates to a method and device for operating and/or testing memory units, which make it possible to conduct a time-saving test of semiconductor memories during running operation. The inventive method for testing memory units having storage locations pr... | 10/23/2007 |
| 7287235 | Method of simplifying a circuit for equivalence checking A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, ... | 10/23/2007 |
| 7278085 | Simple error-correction codes for data buffers A method of and apparatus for handling errors occurring in data stored in memory is presented. Data to be stored in a buffer memory is applied to a generator matrix to generate parity check bits. The parity check bits are stored in the buffer memory along with the d... | 10/02/2007 |
| 7203580 | Electrical control unit and control system comprising plural electrical control units When ENG frames created in an ENG transceiver unit and ECT frames subjected to gateway processing in an ECT gateway processor are transmitted around the same time, a transmission mediating unit alternately transmits each of the ENG frames and the ECT frames. Therefo... | 04/10/2007 |
| 7194673 | Detecting intermittent losses of synchronization in a fibre channel loop Described are a storage system and method for detecting an intermittent loss of synchronization in communication signals received by an enclosure connected to a Fibre Channel loop. A control board produces a first signal representing a status of communication signal... | 03/20/2007 |
| 7193916 | Apparatus and method for determining erasability of data A recording apparatus for facilitating data erasure operations involving data recorded on a recording medium. Each piece of data recorded on the recording medium may be examined to determine whether it is re-recordable by determining whether the data is already stor... | 03/20/2007 |
| 7173858 | Nonvolatile memory and method of driving the same The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh... | 02/06/2007 |
| 7168008 | Method and system for isolating and protecting software components A system and method for protecting software components of a software system can be used to guard against faults which might occur during the execution of a software component. A software component which is particularly prone to faults may be designated for protectio... | 01/23/2007 |
| 7159161 | Test method and architecture for circuits having inputs A test method for a plurality of circuits respectively having inputs for greatly reducing the required test time and the control circuit complexity is provided. The method includes steps of providing a set of test patterns for detecting a characteristic of the circu... | 01/02/2007 |
| 7136316 | Method and apparatus for data compression in memory devices A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pa... | 11/14/2006 |
| 7127650 | Test method and test device for electronic memories A test method for electronic memories includes reading out a previously defined test pattern sequentially as a time-dependent signal from the memory, determining the associated spectrum from the time-dependent signal by Fourier transformation, and assessing the memo... | 10/24/2006 |
| 7116374 | Method and system for enhanced modulation of video signals A method for encoding a carrier signal in a video signal, the video signal having one or more frames, the frames each having a first field and a second field, the first field and the second field of each frame having a plurality of scan lines, each having a pluralit... | 10/03/2006 |
| 7111210 | Accelerated test method for ferroelectric memory device An accelerated test method evaluates, under accelerated conditions (a temperature T2 and a voltage V2), an endurance characteristic of a ferroelectric memory device having a capacitor element including a ferroelectric film under actual operatin... | 09/19/2006 |
| 7102956 | Reduction of fusible links and associated circuitry on memory dies The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number o... | 09/05/2006 |
| 7073071 | Platform and method for generating and utilizing a protected audit log Briefly, one embodiment of a platform for generating and utilizing a protected audit log is described. The platform comprises a system memory and a memory to contain an audit log. The audit log includes a plurality of single-write, multiple read entries. At least on... | 07/04/2006 |
| 7047283 | Apparatus and method of upgrading program of firmware board A program on a firmware board is upgraded without cutting off power or resort to additional firmware writing hardware by providing the board with a flash memory which stores a file for production and a production-processing program for updating the file. A host comp... | 05/16/2006 |
| 7035963 | Method for resolving address space conflicts between a virtual machine monitor and a guest operating system In one embodiment, a method for resolving address space conflicts includes detecting that a guest operating system attempts to access a region occupied by a first portion of a virtual machine monitor and relocating the first portion of the virtual machine monitor wi... | 04/25/2006 |
| 6971053 | Method for initiating internal parity operations in a CAM device A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B) performing an error checking operation for at least one of a plurality of... | 11/29/2005 |
| 6961000 | Smart tag data encoding method A method for storing information in a smart tag comprises providing a smart tag having a memory, the smart tag memory having a permanent number stored in a first portion thereof that cannot be changed, and having a second portion in which information can be stored; ... | 11/01/2005 |
| 6947327 | Nonvolatile memory and method of driving the same The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh... | 09/20/2005 |
| 6799291 | Method and system for detecting a hard failure in a memory array A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a fir... | 09/28/2004 |
| 6754859 | Computer processor read/alter/rewrite optimization cache invalidate signals A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lo... | 06/22/2004 |
| 6732306 | Special programming mode with hashing A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory witho... | 05/04/2004 |
| 6633999 | Integrated circuit with on-chip data checking resources An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The chec... | 10/14/2003 |
| 6553521 | Method for efficient analysis semiconductor failures The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a group of characteristics for a semiconductor of given dimens... | 04/22/2003 |
| 6519694 | System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the... | 02/11/2003 |
| 6510527 | Method and system for data protection A method and a system for data protection of fixed and learned control data of duplicated, program-controlled computers, in which the control parameters are stored in an EEPROM. The memory available in the EEPROM is divided into three areas. Each area is ... | 01/21/2003 |
| 6467056 | Semiconductor integrated circuit and method of checking memory A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for... | 10/15/2002 |
| 6317372 | Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by... | 11/13/2001 |
| 6295618 | Method and apparatus for data compression in memory devices A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coup... | 09/25/2001 |
| 6226766 | Method and apparatus for built-in self-test of smart memories A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any fail... | 05/01/2001 |
