Did You Know...
...that on Dec. 15, 1836, the Patent Office was completely destroyed by fire? Lost were some 7,000 models, 9,000 drawings, and 230 books plus all records of patent applications and grants.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8185787 | Blind and decision directed multi-level channel estimation A technique for blind channel estimation is disclosed herein. A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges and (for each of the bins in the set) a corresponding portion of read values which fall into... | 05/22/2012 |
| 8161333 | Information processing system An information processing system includes a dynamic random access memory, a processor for information processing in cooperation with the dynamic access memory, and a built-in diagnosis module including a longevity evaluation device, the longevity evaluation device c... | 04/17/2012 |
| 8132063 | Semiconductor device To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area includin... | 03/06/2012 |
| 8103922 | Error detection in precharged logic An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker no... | 01/24/2012 |
| 8069382 | Memory cell programming Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes perfo... | 11/29/2011 |
| 8042013 | Semiconductor device and verify method for semiconductor device A semiconductor device includes a memory module provided with a plurality of memory cells, a verify determination unit that performs quality determination of read data that have been read from the memory cells on the basis of the read data and an expected value prep... | 10/18/2011 |
| 8037381 | Error detection, documentation, and correction in a flash memory device A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are era... | 10/11/2011 |
| 8032804 | Systems and methods for monitoring a memory system Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and rep... | 10/04/2011 |
| 8010854 | Method and circuit for brownout detection in a memory system Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations i... | 08/30/2011 |
| 8006147 | Error detection in precharged logic An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker no... | 08/23/2011 |
| 7996735 | Semiconductor device To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area includin... | 08/09/2011 |
| 7945825 | Recovery while programming non-volatile memory (NVM) Disclosed are methods and circuits for performing recovery associated with programming of non-volatile memory (NVM) array cells. According to embodiments, there are provided methods and circuits for programming NVM cells, including: (1) erasing NVM array cells; (2) ... | 05/17/2011 |
| 7853842 | Semiconductor memory device with ZQ calibration A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibratio... | 12/14/2010 |
| 7853841 | Memory cell programming Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes perfo... | 12/14/2010 |
| 7797596 | Method for monitoring and adjusting circuit performance A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical param... | 09/14/2010 |
| 7711998 | Test circuit arrangement A test circuit arrangement for testing latch units is provided which includes a) a voltage generator configured to adjust a voltage potential difference between a first ground line and a second ground line of the latch units and/or to adjust a voltage potential diff... | 05/04/2010 |
| 7707469 | Memory test system including semiconductor memory device suitable for testing an on-die termination, and method thereof Example embodiments relate to a memory test system having a semiconductor memory device, a coupling circuit and a tester. The semiconductor memory device may include a plurality of first output nodes and a plurality of second output nodes. The first output nodes may... | 04/27/2010 |
| 7673195 | Circuits and methods for characterizing device variation in electronic memory circuits A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage grea... | 03/02/2010 |
| 7568135 | Use of alternative value in cell detection A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage represen... | 07/28/2009 |
| 7543199 | Test device A test device that can improve test reliability is provided. In the test device, an error detecting unit detects an error of inputted test signals to generate an error flag, a normal test unit performs a test operation according to the test signals when the error fl... | 06/02/2009 |
| 7496810 | Semiconductor memory device and its data writing method This invention provides a semiconductor memory device and its data writing method capable of saving the needed time to a minimum even in repeating a data write operation maximum number of times. More specifically, this invention provides a semiconductor memory devic... | 02/24/2009 |
| 7478292 | Structure and method for detecting errors in a multilevel memory device with improved programming granularity An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence. Each level representsmg a logic value consisting of a plurality of bits, wherein ... | 01/13/2009 |
| 7457997 | Apparatus and method for detecting over-programming condition in multistate memory device An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed c... | 11/25/2008 |
| 7444563 | Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the ... | 10/28/2008 |
| 7444490 | Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device ... | 10/28/2008 |
| 7444577 | Memory device testing to support address-differentiated refresh rates A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of stor... | 10/28/2008 |
| 7437631 | Soft errors handling in EEPROM devices Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected duri... | 10/14/2008 |
| 7437629 | Method for checking the refresh function of an information memory A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these ... | 10/14/2008 |
| 7415646 | PageEXE erase algorithm for flash memory Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of th... | 08/19/2008 |
| 7409598 | Information storage system A host device 1 includes an NG table 10 for storing addresses specifying areas of a bulk memory 3 into which data cannot be written, a performance-guaranteed environment determination means 11 for determining whether or not the current en... | 08/05/2008 |
| 7398431 | System and method of dynamically setting a fault threshold for an operational module A system and method for determining a fault threshold for an operational module according to the model of the operational module are described. The system includes an operational module, a storage unit, and a monitoring unit. The operational module has circuitry for... | 07/08/2008 |
| 7395480 | Test apparatus and test method The present invention provides a test apparatus comprising: a threshold voltage setting unit for setting threshold voltages of a logic device component connected to the signal propagation path; a test signal supply unit for supplying a test signal to the test subjec... | 07/01/2008 |
| 7395170 | Methods and apparatus for data analysis A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components. ... | 07/01/2008 |
| 7395466 | Method and apparatus to adjust voltage for storage location reliability According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storag... | 07/01/2008 |
| 7392444 | Non-volatile memory evaluating method and non-volatile memory The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with respect to hot holes. The present method performs a write operation to... | 06/24/2008 |
| 7375540 | Process monitor for monitoring and compensating circuit performance A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operati... | 05/20/2008 |
| 7370260 | MRAM having error correction code circuitry and method therefor An embedded memory system (10) uses an MRAM core (12) and error correction code (ECC) corrector circuitry (20). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correct... | 05/06/2008 |
| 7363555 | Memory cell test circuit for use in semiconductor memory device and its method A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the p... | 04/22/2008 |
| 7363556 | Testing apparatus and testing method A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail... | 04/22/2008 |
| 7360112 | Detection and recovery of dropped writes in storage devices Provided are a method, system, and article of manufacture, wherein a request to write data to a storage medium is received. The data requested to be written to the storage medium is stored in a cache. A writing of the data is initiated to the storage medium. A perio... | 04/15/2008 |
