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| Number | Title | Issue Date |
| 8001432 | Uninitialized memory detection using error correction codes and built-in self test An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular locatio... | 08/16/2011 |
| 7971113 | Method for detecting disturb phenomena between neighboring blocks in non-volatile memory A method for detecting disturb phenomena between neighboring blocks in non-volatile memory includes, sequentially erasing and writing test data (pattern) to each block of a plurality of blocks under test in the non-volatile memory at a first time point, dividing the... | 06/28/2011 |
| 7971114 | Method for testing a memory device A method for testing a random-access memory (RAM) includes six tests. The first test is performed by performing a write and read test to storage locations of the RAM. The second test is performed by testing walking 1's across each data bus of the RAM. The third test... | 06/28/2011 |
| 7949911 | Method for testing storage apparatus and system thereof A method for testing a storage apparatus, which includes: (a) writing a specific pattern to a storage unit of a storage apparatus; (b) reading the specific pattern written to the storage apparatus; (c) determining an error bit number of the specific pattern read in ... | 05/24/2011 |
| 7681096 | Semiconductor integrated circuit, BIST circuit, design program of BIST circuit, design device of BIST circuit and test method of memory A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately g... | 03/16/2010 |
| 7631233 | Data inversion register technique for integrated circuit memory testing A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the pres... | 12/08/2009 |
| 7627793 | Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first ... | 12/01/2009 |
| 7454672 | Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator config... | 11/18/2008 |
| 7441169 | Semiconductor integrated circuit with test circuit A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for conne... | 10/21/2008 |
| 7433252 | Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconduct... | 10/07/2008 |
| 7428682 | Semiconductor memory device In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and ... | 09/23/2008 |
| 7426668 | Performing memory built-in-self-test (MBIST) Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... | 09/16/2008 |
| 7421629 | Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to co... | 09/02/2008 |
| 7417814 | Magnetic recording device A magnetic recording device comprising a magnetic recording medium, a read-write channel for modulating write data, writing it on the magnetic recording medium, reading data from the magnetic recording medium, and demodulating the read data, and a processor for supp... | 08/26/2008 |
| 7415649 | Semi-conductor component test device with shift register, and semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-condu... | 08/19/2008 |
| 7412619 | Integrated circuit capable of error management A method according to one embodiment may include receiving a write request to write data in a local storage device. The method of this embodiment may also include detecting a write error in the local storage device. The method of this embodiment may also include res... | 08/12/2008 |
| 7386650 | Memory test circuit with data expander A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the expanded test pattern data into a memory having the second data width... | 06/10/2008 |
| 7376889 | Memory device capable of detecting its failure A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data inp... | 05/20/2008 |
| 7366967 | Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices Methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pa... | 04/29/2008 |
| 7362089 | Carrier module for adapting non-standard instrument cards to test systems A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test ... | 04/22/2008 |
| 7363533 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit ser... | 04/22/2008 |
| 7360116 | Built-in self test circuit A built-in self test circuit (BIST circuit) in an LSI includes a verification test pattern generator for generating verification test pattern which is used for verifying the connections in the LSI including the BIST circuit in the design stage thereof, and another t... | 04/15/2008 |
| 7353438 | Transparent error correcting memory A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory ... | 04/01/2008 |
| 7346817 | Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first ... | 03/18/2008 |
| 7343532 | Testing memory units in a digital circuit A method of testing a memory unit in a digital circuit includes storing a test pattern on a register of the digital circuit. The register is then selected by providing an activation signal to a selection unit. The memory unit is then tested with the test pattern sto... | 03/11/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7328365 | System and method for providing error check and correction in memory systems A system for providing error check and correction (ECC) is provided. The system includes an ECC interface for storing ECC codes in a first memory system and storing data in a second memory system. The ECC interface corrects errors in the data received from the secon... | 02/05/2008 |
| 7324392 | ROM-based memory testing This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These re... | 01/29/2008 |
| 7325176 | System and method for accelerated information handling system memory testing Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instanc... | 01/29/2008 |
| 7324391 | Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback A method (200) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit fail... | 01/29/2008 |
| 7321521 | Assessing energy requirements for a refreshed device Method and apparatus for assessing a time interval during which a refresh device can be maintained in a self-refresh mode by an associated energy source. The refresh device is initially operated in a self-refresh mode to maintain the device in a selected state. The ... | 01/22/2008 |
| 7321951 | Method for testing flash memory power loss recovery Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point to interrupt/stop execution or simulate power loss at a specific poi... | 01/22/2008 |
| 7319623 | Method for isolating a failure site in a wordline in a memory array According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordlin... | 01/15/2008 |
| 7313739 | Method and apparatus for testing embedded cores Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an ad... | 12/25/2007 |
| 7304901 | Enabling memory redundancy during testing Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements... | 12/04/2007 |
| 7294998 | Timing generation circuit and semiconductor test device having the timing generation circuit A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 | 11/13/2007 |
| 7293206 | Test data pattern for testing a CRC algorithm A method of generating a test data pattern for testing a CRC algorithm, the CRC algorithm configured to generate CRC values based on a generator polynomial, the method including identifying a desired pattern of intermediate CRC values. The method includes generating... | 11/06/2007 |
| 7293221 | Methods and systems for detecting memory address transfer errors in an address bus A method for detecting transfer errors in an address bus is provided. In this method, a first address parity is generated using a memory address. Next, at least two data error-correction-code (ECC) check bits are scrambled using the first address parity. Subsequentl... | 11/06/2007 |
| 7293199 | Method and apparatus for testing memories with different read/write protocols using the same programmable memory bist controller A method of testing a plurality of embedded memories within an integrated circuit. Each of the embedded memories include particular read and write protocols. The method includes providing a memory built in self test sequencer module and providing satellite engine mo... | 11/06/2007 |
| 7290186 | Method and apparatus for a command based bist for testing memories Methods and apparatuses in which two or more memories share a processor for Built In Self Test algorithms and features are described. The processor initiates a Built In Self Test for the memories. Each memory has an intelligence wrapper bounding that memory. Each in... | 10/30/2007 |
