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| Number | Title | Issue Date |
| 8176372 | Semiconductor integrated circuit A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an... | 05/08/2012 |
| 8166356 | Memory system and memory access method A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data th... | 04/24/2012 |
| 8151150 | Data storage device and method for writing test data to a memory The invention provides a method for writing test data to a memory. In one embodiment, the memory comprises a data register. First, test data is written to a memory space of the memory. A read-back command and a read-back address of the memory space are then sent to ... | 04/03/2012 |
| 8140921 | System for elevator electronic safety device An elevator electronic safety system in which reliability of malfunction check can be improved by performing a malfunction check on memory data, an address bus, and a data bus. A check on the address bus and the data bus is executed periodically by a hardware circui... | 03/20/2012 |
| 8122307 | One time programmable memory test structures and methods One Time Programmable (OTP) memory structures and methods for pretesting the support circuitry are provided. A group of dedicated test cells associated with one or more groups of regular OTP cells are used to test the support circuitry for the regular OTP cells. The... | 02/21/2012 |
| 8108741 | Semiconductor memory device having mount test circuits and mount test method thereof A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least... | 01/31/2012 |
| 8086918 | High-speed serial transfer device test data storage medium and device A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according to a code conversion table are successively transferred to each of a plurality of serial transfer channels ... | 12/27/2011 |
| 8082476 | Program verify method for OTP memories A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data. In a program operation, the master latch stores program data which is ... | 12/20/2011 |
| 8032803 | Semiconductor integrated circuit and test system thereof A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to w... | 10/04/2011 |
| 8015460 | Test mode for parallel load of address dependent data to enable loading of desired data backgrounds One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention... | 09/06/2011 |
| 8010853 | Semiconductor storage device and memory test circuit Each of a plurality of nonmatching detection circuits is provided for each bit, compares bit output of memory with an expected value corresponding to the bit output, and outputs a nonmatching detection signal when the bit output does not match the value. A selection... | 08/30/2011 |
| 8006146 | Test apparatus and test method for testing a plurality of devices under test Provided is a test apparatus for testing a plurality of devices under test, the test apparatus including: a data supplying section that concurrently supplies test data to the plurality of devices under test; a writing control section that controls the test data to b... | 08/23/2011 |
| 7979761 | Memory test device and memory test method A memory test device, including a universal register to conduct an operation by a predetermined universal command language; an extension register having a larger capacity than the universal register and to conduct an operation by a predetermined extension command la... | 07/12/2011 |
| 7975192 | Reading memory cells using multiple thresholds A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog me... | 07/05/2011 |
| 7971112 | Memory diagnosis method A method of an apparatus for diagnosing a memory including a storing module for storing diagnosis information relating to memory errors in a memory to be diagnosed, the apparatus capable of detecting memory errors, the method includes: testing the memory and detecti... | 06/28/2011 |
| 7966531 | Memory diagnosis apparatus A memory diagnosis apparatus include an intra-word testing unit that tests for a coupling fault in each bit in each word in a memory, an inter-word testing unit that tests for a coupling fault between words in each sub-array each being plural words in the memory, an... | 06/21/2011 |
| 7958415 | Semiconductor integrated circuit and method of detecting fail path thereof Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value an... | 06/07/2011 |
| 7954020 | Method and apparatus for testing a circuit A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a success... | 05/31/2011 |
| 7941714 | Parallel bit test apparatus and parallel bit test method capable of reducing test time A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals pro... | 05/10/2011 |
| 7921341 | System and method for reproducing memory error An information processing apparatus includes a nonvolatile memory area having a storage area, and a main controller configured to store an access pattern to a main memory in the nonvolatile memory area, to end the storage of the access pattern when an error is detec... | 04/05/2011 |
| 7913130 | Multi-sample read circuit having test mode of operation A data storage device includes non-volatile memory; and a read circuit for performing multi-sample read operations on the memory during a normal mode of operation. The read circuit includes a digital counter having an output that indicates a single bit (e.g., a sign... | 03/22/2011 |
| 7900102 | High-speed programming of memory devices A method for operating a memory that includes a plurality of analog memory cells includes storing data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group. After storing the data, respective second cell... | 03/01/2011 |
| 7882408 | Real time feedback compensation of programmable logic memory Memory performance in programmable logic is significantly increased by adjusting a timing of control signals sent to a memory to compensate for variations in process, voltage, or temperature. A calibration circuit can adjust the control signal timing, dynamically an... | 02/01/2011 |
| 7865787 | Testing embedded circuits with the aid of a separate supply voltage Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circui... | 01/04/2011 |
| 7814381 | Semiconductor memory device A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the... | 10/12/2010 |
| 7797595 | Serially decoded digital device testing Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection... | 09/14/2010 |
| 7797594 | Built-in self-test of 3-dimensional semiconductor memory arrays A method and apparatus for testing a three dimensional (3D) memory including a static array and an active array. The method is performed by a memory built-in self-test (MBIST) controller, and includes writing data to the static array, transferring data from the stat... | 09/14/2010 |
| 7783944 | Semiconductor memory device and method thereof A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at l... | 08/24/2010 |
| 7779316 | Method of testing memory array at operational speed using scan A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of th... | 08/17/2010 |
| 7779315 | Semiconductor memory device having a single input terminal to select a buffer and method of testing the same A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminal... | 08/17/2010 |
| 7765442 | Memory device testable without using data and dataless test method Example embodiments of the present invention include a memory device testable without using data and a dataless test method. The memory device includes a plurality of registers to store test patterns, the registers being coupled to input/output DQ pads. The test pat... | 07/27/2010 |
| 7757134 | Test apparatus for testing a memory and electronic device housing a circuit A test apparatus for testing a memory under test is provided, including a pattern generator generating a read address from which data is read from the memory under test and an expected value of the data read from the read address, a logical comparator comparing the ... | 07/13/2010 |
| 7743292 | Apparatus and method for memory card testing The invention provides a memory card testing apparatus for performing automated operations on memory cards. The memory card testing apparatus comprises a host device, a database, a processing unit and an interface. The host device is provided for accessing a memory ... | 06/22/2010 |
| 7734967 | Semiconductor memory device and testing method of the same A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, eac... | 06/08/2010 |
| 7685480 | Content addressable memory having redundant row isolated noise circuit and method of use A system and method are provided for reducing the capacitive coupling noise on a fuse line of a content addressable memory (CAM) system. The CAM system includes a plurality of CAM arrays having a plurality of rows of CAM cells to store data coupled to wordlines, sea... | 03/23/2010 |
| 7676709 | Self-test output for high-density BIST A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the one or more memories to perform write operation and to receive a PASS/F... | 03/09/2010 |
| 7640467 | Semiconductor memory with a circuit for testing the same Upon conduct of a test on a semiconductor memory in a merged LSI or the like, data signals from a small data bus width are simultaneously written to a plurality of memory cells of a memory core. Then, a coincidence detection circuit makes a comparison between data r... | 12/29/2009 |
| 7624317 | Parallel bit test circuit and method for semiconductor memory device A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory blo... | 11/24/2009 |
| 7617425 | Method for at-speed testing of memory interface using scan A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory loc... | 11/10/2009 |
| 7607055 | Semiconductor memory device and method of testing the same A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the recei... | 10/20/2009 |
