Bizarre Patents
Neuroimaging as a Marketing Tool
Neuroimaging as a means for validating whether a stimulus such as advertisement, communication, or product evokes a certain mental response such as emotion, preference, or memory, or to predict the consequences of the stimulus on later behavior such as consumption or purchasing.
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| Number | Title | Issue Date |
| 8135999 | Disabling outbound drivers for a last memory buffer on a memory channel Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plura... | 03/13/2012 |
| 8122305 | Standalone data storage device electromagnetic interference test setup and procedure A system for operating a data storage device having a plurality of sectors and at least one port, each port having a transmitter and a receiver, is disclosed. In one embodiment the system includes coupling at least one of the transmitters to at least one of the rece... | 02/21/2012 |
| 8086915 | Memory controller with loopback test interface In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operati... | 12/27/2011 |
| 8015458 | Fault isolation in interconnect systems A loopback connector for a system can include a connector arrangement connectable to connector of a system component and/or a cable. The loopback connector can include loopback logic for simulating cable and/or system component functionality. In an example implement... | 09/06/2011 |
| 7971110 | System and method for testing a serial attached small computer system interface In a system and method for testing a serial attached small computer systems (SAS) interface of a SAS controller, the SAS controller connects to a loopback dongle via the SAS interface. The SAS interface sends a first data packet to the loopback dongle, and receives ... | 06/28/2011 |
| 7962808 | Method and system for testing the compliance of PCIE expansion systems The present application describes a method and system for testing the compliance of a PCIE expansion system to verify that data signals transmitted through multiple data lanes in the expansion system comply with the PCIE requirements. The method for testing a PCIE e... | 06/14/2011 |
| 7882404 | Backplane emulation technique for automated testing The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitte... | 02/01/2011 |
| 7730367 | Method and system for testing devices using loop-back pseudo random data There is provided a method of testing a first device using a tester. The method includes receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device,... | 06/01/2010 |
| 7716540 | Standalone data storage device electromagnetic interference test setup and procedure A data storage device includes a plurality of sectors and a port, the port having a transmitter and a receiver. In one embodiment a method includes coupling the transmitter to receiver, providing power to the data storage device, detecting that the transmitter is co... | 05/11/2010 |
| 7681093 | Redundant acknowledgment in loopback entry Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example the acknowledgment is performed by initiating loopback communications from a first agent to a second agent, sending a packet includi... | 03/16/2010 |
| 7657799 | Method and apparatus for testing a dual mode interface Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operatio... | 02/02/2010 |
| 7653844 | Communication apparatus and communication system In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmi... | 01/26/2010 |
| 7650540 | Detecting and differentiating SATA loopback modes A method according to one embodiment may include communicating, by a far end device with a near end device, using a Serial ATA (SATA) communications protocol; receiving, by the far end device, a SATA signal sequence having two bits, the state of which define at leas... | 01/19/2010 |
| 7620858 | Fabric-based high speed serial crossbar switch for ATE A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to... | 11/17/2009 |
| 7484139 | Amplifier fault detection circuit An amplifier (1) adapted to receive an input signal and to generate an output signal at an amplifier output (7) according to the input signal, the amplifier (1) comprising: a feedback circuit arranged to provide a feedback signal indicative of t... | 01/27/2009 |
| 7447953 | Lane testing with variable mapping Memory apparatus and methods selectively map first lanes to second lanes. A memory agent may transfer training and return sequences using different lane mappings. The return sequences may be analyzed to identify failed lanes. Other embodiments are described and clai... | 11/04/2008 |
| 7444558 | Programmable measurement mode for a serial point to point link A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and ... | 10/28/2008 |
| 7437628 | Data transmission apparatus and method A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at leas... | 10/14/2008 |
| 7426599 | Systems and methods for writing data with a FIFO interface Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I... | 09/16/2008 |
| 7424649 | Latch and phase synchronization circuit using same A latch is provided for rapidly stabilizing a latching operation. The latch comprises a first latch circuit for latching a first signal in response to a first portion of a second signal to generate a first latch signal, and a latch error compensator for compensating... | 09/09/2008 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 7386767 | Programmable bit error rate monitor for serial interface A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag ge... | 06/10/2008 |
| 7380152 | Daisy chained multi-device system and operating method A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the dais... | 05/27/2008 |
| 7373622 | Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed ar... | 05/13/2008 |
| 7373577 | CAN system Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error d... | 05/13/2008 |
| 7366964 | Method, system, and apparatus for loopback entry and exit A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to... | 04/29/2008 |
| 7360127 | Method and apparatus for evaluating and optimizing a signaling system A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive... | 04/15/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7360129 | Simultaneous switch test mode The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS test mode data is driven on a data bus during an idle bus period. Otherwise, when SS test mode is disabl... | 04/15/2008 |
| 7356024 | Communication apparatus and communication method A correlation memory section 105 stores a prescribed table in which each control data is grouped for each kind of it (for each message unit) to be correlated to each other. A control data synchronization section 104 successively accumulates input contr... | 04/08/2008 |
| 7353154 | Customer controlled design of a communication system A system for designing a communication link for use in a data processing system, includes a parameter generator and an internal link model. The parameter generator allows a user to specify a first set of link parameters. The generator derives a set of internal param... | 04/01/2008 |
| 7346819 | Through-core self-test with multiple loopbacks An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data s... | 03/18/2008 |
| 7340662 | GBit/s transceiver with built-in self test features GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a transmit portion and a receive portion, the analog portions adaptable to in... | 03/04/2008 |
| 7336673 | Creating a low bandwidth channel within a high bandwidth packet stream Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra pa... | 02/26/2008 |
| 7337377 | Enhanced loopback testing of serial devices A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The... | 02/26/2008 |
| 7336749 | Statistical margin test methods and circuits Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique ... | 02/26/2008 |
| 7327672 | Signal routing in a node of a 1:N automatic protection switching network Automatic protection switching is implemented by channel devices in a data communication system node. Each channel devices includes input and output ports, a data receive port, a data send port, and a signal routing arrangement controlled by a processor element. The... | 02/05/2008 |
| 7325180 | System and method to test integrated circuits on a wafer A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on a... | 01/29/2008 |
| 7313178 | Transceiver for receiving and transmitting data over a network and method for testing the same The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, ... | 12/25/2007 |
| 7313738 | System and method for system-on-chip interconnect verification A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip componen... | 12/25/2007 |
