Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 8117508 | Non-volatile memory device and programming method thereof A non-volatile memory device including: a memory cell array storing an electrically rewritable resistance value as data in a non-volatile manner; a first cache circuit configured to hold program data to be programmed in the cell array; a second cache circuit configu... | 02/14/2012 |
| 8082475 | Enhanced microprocessor interconnect with bit shadowing Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is us... | 12/20/2011 |
| 8082474 | Bit shadowing in a memory system Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition, shadow compare logic is u... | 12/20/2011 |
| 8074126 | Non-intrusive eye monitor system A signal receiver includes a data recovery module that generates an equalized data signal and a recovered data signal based on a data input signal. An error module generates an error information signal based on the equalized data signal and an error threshold signal... | 12/06/2011 |
| 8074127 | Signal analyzing apparatus The present invention is to provide a signal analyzing apparatus which can easily identify a pattern high in error rate and a pattern causing bit errors in comparison with the conventional device. In a signal analyzing apparatus (4) for analyzing a signal fro... | 12/06/2011 |
| 8060797 | Semiconductor storage device A semiconductor storage device can efficiently perform a refresh operation. A semiconductor storage device is provided which includes a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing. A controlling unit is further in... | 11/15/2011 |
| 8060796 | Multiplexing method and apparatus thereof for data switching A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even ... | 11/15/2011 |
| 8051338 | Inter-asic data transport using link control block manager An apparatus includes a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking ... | 11/01/2011 |
| 8037374 | Communication terminal device and reception environment reporting method A communication terminal device and a reception environment reporting method produce a more excellent throughput, by making a report of a reception environment with higher accuracy. An SIR measuring section measures an SIR from a reception signal that has been recei... | 10/11/2011 |
| 8024625 | Network system for diagnosing operational abnormality of nodes A network system for judging abnormality of a self node with high precision on the basis of information from other nodes connected to a network is provided. In each node, a frequency at which data frames to be transmitted/received among nodes cannot be received is c... | 09/20/2011 |
| 8015539 | Method and apparatus for performance metric compatible control of data transmission signals The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a differential signal as received by a receiver of a data transmission... | 09/06/2011 |
| 8006141 | Method for speeding up serial data tolerance testing A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, wh... | 08/23/2011 |
| 8006142 | GPON Rogue-ONU detection based on error counts A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a global error-counter, coupled to the OLT, for counting FEC-correctable errors, for each ONU, from a data stream from the GPON; and a CPU for extracting an ONU statu... | 08/23/2011 |
| 7987395 | Evaluation method of random error distribution and evaluation apparatus thereof A degree of conformity of error distribution of a digital signal to the Poisson distribution is quantitatively determined. The digital signal including error data, which is randomly generated at a predetermined error rate, is divided into data number of measurement ... | 07/26/2011 |
| 7987396 | Reducing bit-error rate using adaptive decision feedback equalization The present specification describes techniques and apparatus that adjust filter tap values to be used in filtering a data value input to a detector and/or that increase or decrease a threshold value used to determine whether to adjust the filter tap values. ... | 07/26/2011 |
| 7984341 | Method, system and computer program product involving error thresholds A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, incremen... | 07/19/2011 |
| 7984342 | System and method for MPEG CRC error based video network fault detection Disclosed herein are systems, methods, and computer readable-media for detecting and identifying network faults. The method includes recording cyclic redundancy check (CRC) errors gathered by a data stream analyzer, if the number of CRC errors exceeds a threshold, s... | 07/19/2011 |
| 7979754 | Voltage margin testing for proximity communication A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by jux... | 07/12/2011 |
| 7975189 | Error rate estimation/application to code-rate adaption The disclosure proposes bit-error-rate (BER) and symbol-error-rate (SER) estimation techniques and its application to incremental-redundancy and rate-adaptation for modern-coded hybrid-ARQ systems. In particular, BER/SER estimators are proposed based on iterative re... | 07/05/2011 |
| 7971107 | Calculation apparatus, calculation method, program, recording medium, test system and electronic device A calculating apparatus that calculates a characteristic of a target signal, including an input section that receives a bit error or a sampling timing, and a calculating section that calculates sampling timings over a range in which the bit error rate is less than a... | 06/28/2011 |
| 7971108 | Modem-assisted bit error concealment for audio communications systems Systems and methods are described for managing bit errors present in a series of encoded bits representative of a portion of an audio signal, wherein the series of encoded bits is received over a communication link in an audio communications system. At least one cha... | 06/28/2011 |
| 7962806 | Method and system for providing bit error rate characterization An approach is provided for bit error rate characterization. A test signal representing one or more Ethernet frames exhibiting a particular bit error rate is generated. The test signal is output to a device under test. Traffic is received from the device under test.... | 06/14/2011 |
| 7962805 | System and method for preventing a race condition A system that includes a first flip flop that is serially coupled to a second flip flop. The first flip flop includes a transfer circuit that is coupled between a master latch and a slave latch. The master latch of the first flip flop latches a scan data signal duri... | 06/14/2011 |
| 7933909 | Systems and methods for improving the linkage and security of records A system and method for improving the linkage and security of records is provided. Generally, the present invention can be viewed as providing methods for selecting an ideal identifier, from a series of test identifiers, for linking more than one associated record. ... | 04/26/2011 |
| 7925936 | Memory device with non-uniform programming levels A method for storing data in a memory, which includes a plurality of analog memory cells, includes defining programming levels that represent respective combinations of at least first and second bits and are represented by respective nominal storage values. The data... | 04/12/2011 |
| 7904763 | Reception device, reception method, information processing device, information processing method, and program A reception device configured to receive a signal of a transmitted bit string transmitted from a transmission device which transmits a bit string includes: a receiving unit arranged to receive a signal from the transmission device and output a received bit string co... | 03/08/2011 |
| 7904762 | Error detection on medical high speed transmission routes In a transmission error logging device, method and computer-readable medium for logging transmission errors that occur on a high speed transmission route of a medical technology diagnostic apparatus, the in-feed port for a signal is provided on the high speed transm... | 03/08/2011 |
| 7895480 | Method for testing the error ratio BER of a device according to confidence level, test time and selectivity A method for testing the error ratio BER of a device under test against a specified allowable error ratio comprises the steps: measuring ns samples of the output of the device, thereby detecting ne erroneous samples of these ns samples, defining BER(ne)=ne/ns as the... | 02/22/2011 |
| 7890818 | Read level control apparatuses and methods Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a b... | 02/15/2011 |
| 7870445 | System and method for measuring and depicting performance of a serial communications link A system for measuring performance of a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the recei... | 01/11/2011 |
| 7853837 | Memory controller and method for operating a memory controller having an integrated bit error rate circuit A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to a... | 12/14/2010 |
| 7827450 | Defect detection and handling for memory based on pilot cells A memory system includes a first parameter estimation module that receives pilot signals that are generated based on pilot data stored in a memory. The first parameter estimate module generates a first estimate of a signal quality value associated with a block of th... | 11/02/2010 |
| 7818634 | Detecting method and system for consistency of link scrambling configuration A detecting method for the consistency of a link scrambling configuration, comprises: setting the first threshold of the data packet error rate received by the receiving end; when the receiving end receiving date from the link, counting the received data packet erro... | 10/19/2010 |
| 7809996 | Adaptive FEC codeword management Adaptive FEC coding is used to adjust the codeword composition of FEC codewords in a communication system. A codeword composition ratio may be adjusted in response to variance of a measured transmission error value from a target transmission error value in the syste... | 10/05/2010 |
| 7793171 | Protocol tester and method for performing a protocol test Embodiments of the present invention provide a protocol tester for performing a protocol test, said protocol tester exhibiting an input for the feeding in of data, a protocol decoding device for the decoding of data, and an output for providing the decoded data, the... | 09/07/2010 |
| 7788547 | Systems and methods for generation of communication channel fault information A method is provided for generating fault information associated with a communication channel. In the method, a time-varying error value associated with the communication channel is received. If the error value exceeds a first threshold, a first time value associate... | 08/31/2010 |
| 7743289 | Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage n... | 06/22/2010 |
| 7743288 | Built-in at-speed bit error ratio tester A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (... | 06/22/2010 |
| 7739558 | Method and apparatus for rectifying errors in the presence of known trapping sets in iterative decoders and expedited bit error rate testing A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associa... | 06/15/2010 |
| 7721162 | System for testing the upstream channel of a cable network A system for testing a portion of a cable network provides a pattern generator, Addresser, forward error corrector, and comparator. The system is particularly adapted to testing the upstream channel in a cable network. The pattern generator generates a test signal. ... | 05/18/2010 |
