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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 8028206 | Memory device including memory controller A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and... | 09/27/2011 |
| 7904761 | Method and apparatus for a discrete power series generator A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity PSV generator, such that the need for multiplication operations is ob... | 03/08/2011 |
| 7886203 | Method and apparatus for bit interleaving and deinterleaving in wireless communication systems Disclosed herein is a method and system for interleaving and deinterleaving of data bits in wireless data communications. Interleaving is performed as a single stage parallel operation using a single standard memory block. The disclosed method and system is capable ... | 02/08/2011 |
| 7831869 | DDS logical data grouping A block of user data is formatted by arranging the user data block into a byte array having plural rows and plural columns of bytes. An error correction code is applied to individual ones of the rows of bytes, such that each row has four code words. ... | 11/09/2010 |
| 7793170 | Method and apparatus for combining de-interleaving with FFT and demapping A novel technique for combining deinterleaving operation with Fast Fourier Transformer (FFT) modules and other post FFT modules in a receiver to reduce processing time. In one example embodiment, the deinterleaving operation, in the post FFT module, is combined with... | 09/07/2010 |
| 7765441 | Methods and systems for detecting symbol erasures A technique for determining a symbol erasure threshold for a received communication signal containing symbol information begins by performing a first threshold calculation to produce an initial symbol erasure threshold, then performing a first margin calculation to ... | 07/27/2010 |
| 7743287 | Using SAM in error correcting code encoder and decoder implementations SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward E... | 06/22/2010 |
| 7702970 | Method and apparatus for deinterleaving interleaved data stream in a communication system An apparatus and method for reading written symbols by deinterleaving to decode a written encoder packet in a receiver for a mobile communication system supporting turbo coding and interleaving, such that a turbo-coded/interleaved encoder packet has a bit shift valu... | 04/20/2010 |
| 7577881 | Method and apparatus for an interleaver A modem configured to couple to a communication medium for establishing a communication channel thereon. The modem includes an interleaver component configurable as to interleaver parameters ‘I, D’ corresponding to block length and depth respectively. An interle... | 08/18/2009 |
| 7555684 | Circuit for and a method of generating an interleaver address A method of generating interleaver addresses in a circuit for decoding data is disclosed. The method comprises the steps of receiving a data stream having a plurality of data blocks, each block having N bits; dividing each data block of the plurality of data blocks ... | 06/30/2009 |
| 7549093 | Method for changing a depth of an interleaver device or de-interleaver device and corresponding interleaver device and de-interleaver device Methods for changing a depth of interleaver devices and de-interleaver devices are provided, whereby a change in the depth is possible while transmitting or receiving operations are in progress. For this, delays of delaying devices are enlarged or reduced, additiona... | 06/16/2009 |
| 7529985 | Memory size allocation device and method for interleaving A method and device for interleaving the (N+1) input data and for allocating the corresponding memory comprises the steps of allocating a mth buffer section equals to (m×Dm+Pm) memory address for buffering the mth data of the N+1 input data, w... | 05/05/2009 |
| 7447950 | Memory device and memory error correction method In a memory system, an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order ... | 11/04/2008 |
| 7444580 | System and method for interleaving data in a communication device A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. A write module is configured to receive a burst of data and write blocks of data from the burst into the memor... | 10/28/2008 |
| 7444556 | System and method of interleaving transmitted data A method (500) is provided for operating an interleaver circuit 120 having N shift lines (2201-220N). Each shift line has a line input node, a line output node, and one or more bit storage elements (240). The ... | 10/28/2008 |
| 7434115 | Encoding and decoding apparatus and method An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encod... | 10/07/2008 |
| 7426663 | Semiconductor integrated circuit and testing method thereof There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also... | 09/16/2008 |
| 7421629 | Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to co... | 09/02/2008 |
| 7415649 | Semi-conductor component test device with shift register, and semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-condu... | 08/19/2008 |
| 7409607 | Memory address generating apparatus, processor having the same, and memory address generating method A memory address generating apparatus comprising an address converting circuit, after setting a first setting region storing substitution source data and a second setting region storing substitution destination data that are a substitution target of the substitution... | 08/05/2008 |
| 7404131 | High efficiency, error minimizing coding strategy method and apparatus A method for creating a high efficiency, error minimizing code is provided. In addition, an apparatus having a high efficiency, error minimizing code is provided. In particular, the present invention provides a high efficiency, error minimizing code for use in conne... | 07/22/2008 |
| 7395461 | Low complexity pseudo-random interleaver An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The inter... | 07/01/2008 |
| 7394412 | Unified interleaver/de-interleaver An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector,... | 07/01/2008 |
| 7386766 | Address generation apparatus for turbo interleaver and deinterleaver in W-CDMA systems There is provided an address generation apparatus for one of an interleaver and a deinterleaver in a Wideband Code Division Multiple Access (W-CDMA) system. The apparatus includes an address pair generator for generating an address pair (n, P(n)) in real-time for on... | 06/10/2008 |
| 7376888 | Interleaved recording of separated error correction encoded information An error correction code system, e.g. of a magnetic tape drive, applies error correction redundancy to data, separates it, or interleaves it, and records it into separate groups. An error correction encoder applies an outer error correction code to one of the separa... | 05/20/2008 |
| 7370252 | Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory u... | 05/06/2008 |
| 7366962 | Interleaving/deinterleaving method and apparatus An interleaving/deinterleaving method and apparatus may interleave/deinterleave first data to produce second data so that the arrangement of data elements of the second data is different from that of the first data. To accomplish this, word data that are part of the... | 04/29/2008 |
| 7363552 | Method and apparatus for convolutional interleaving/de-interleaving technique The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution inter... | 04/22/2008 |
| 7360147 | Second stage SOVA detector A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The se... | 04/15/2008 |
| 7353344 | Storage device The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas q... | 04/01/2008 |
| 7353438 | Transparent error correcting memory A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory ... | 04/01/2008 |
| 7352817 | Method and apparatus for interleaving signal bits in a digital audio broadcasting system This invention provides a method for interleaving bits of a digital signal representative of data and/or audio in a digital audio broadcasting system, the method comprising the step of: writing a plurality of bits of the digital signal to a matrix; and reading the b... | 04/01/2008 |
| 7349271 | Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that... | 03/25/2008 |
| 7346736 | Selecting basis functions to form a regression model for cache performance One embodiment of the present invention provides a system that selects bases to form a regression model for cache performance. During operation, the system receives empirical data for a cache rate. The system also receives derivative constraints for the cache rate. ... | 03/18/2008 |
| 7343531 | Method for interleaving data frame and circuit thereof A method, adapted to a 3GPP turbo coder, for interleaving a plurality of data of a data frame and a circuit thereof is provided. The present invention computes a value of Row Parameter according to the size of the data frame, computes an index for a table according ... | 03/11/2008 |
| 7343530 | Turbo decoder and turbo interleaver A processor on which a software-based interleaver is run performs interleaver generation, which is split into two parts to reduce the overhead time of interleaver changing. First, preprocessing prepares seed variables, requiring a small memory. Second, on-the-fly ad... | 03/11/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7340669 | Memory efficient streamlined transmitter with a multiple instance hybrid ARQ An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal in response to a first intermediate signal and a second intermediate signal. The second intermediate signal comprises a se... | 03/04/2008 |
| 7331011 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second... | 02/12/2008 |
| 7328317 | Memory controller and method for optimized read/modify/write performance A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embo... | 02/05/2008 |
