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| Number | Title | Issue Date |
| 8171353 | System and method for initializing a memory system, and memory device and processor-based system using same Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane ske... | 05/01/2012 |
| 8161331 | Data training system and method thereof A data training system and method thereof are provided. The example data training system may include a memory controller transmitting a given data pattern to a memory device, the memory controller first determining whether an error is present within the transmitted ... | 04/17/2012 |
| 8108738 | Data eye monitor method and apparatus An apparatus and method for providing a data eye monitor. The data eye monitor apparatus utilizes an inverter/latch string circuit and a set of latches to save the data eye for providing an infinite persistent data eye. In operation, incoming read data signals are a... | 01/31/2012 |
| 8103917 | Circuit and method for correcting skew in a plurality of communication channels for communicating with a memory device, memory controller, system and method using the same, and memory test system and method using the same In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and in a memory system and method, the circuit for correcting skew includes... | 01/24/2012 |
| 8074125 | Apparatus and method for transmitting and receiving data bits Provided are an apparatus and method for transmitting and receiving data bits. The apparatus includes a transmitter configured to generate a transmission signal corresponding to the data bits and having a periodic transition, a data line configured to transmit the g... | 12/06/2011 |
| 8037370 | Data transmission apparatus with information skew and redundant control information and method Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circ... | 10/11/2011 |
| 8037372 | Apparatus and method for testing setup/hold time An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to g... | 10/11/2011 |
| 8037371 | Apparatus and method for testing high-speed serial transmitters and other devices A testing device for testing a high-speed serial transmitter or other device includes an input stage having a first comparator, a second comparator, and a digital-to-analog converter. The first comparator compares first differential signals from a device under test.... | 10/11/2011 |
| 8024623 | Misalignment compensation for proximity communication In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. T... | 09/20/2011 |
| 7949907 | Method and device for data communication A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The dev... | 05/24/2011 |
| 7945821 | Time lag measuring device, distance measuring apparatus and distance measuring method In measuring a certain time lag between generations of two pulse signals, a time lag measuring device prevents errors in measurement results even with an error in two reference signals for measuring the time lag. The device measures a time lag between a start signal... | 05/17/2011 |
| 7895479 | System and method for initializing a memory system, and memory device and processor-based system using same Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane ske... | 02/22/2011 |
| 7870444 | System and method for measuring and correcting data lane skews A system and method for measuring and correcting data lane skews uses a predefined datum within data streams transmitted on different data lanes to determine the fastest data lane and to compute relative data lane skew values for the data lanes with respect to the f... | 01/11/2011 |
| 7856578 | Strobe technique for test of digital signal timing A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can ... | 12/21/2010 |
| 7853836 | Semiconductor integrated circuit A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which sampl... | 12/14/2010 |
| 7849371 | Time lag measuring device, distance measuring apparatus and distance measuring method In measuring a certain time lag between generations of two pulse signals, a time lag measuring device prevents errors in measurement results even with an error in two reference signals for measuring the time lag. The device measures a time lag between a start signal... | 12/07/2010 |
| 7849370 | Jitter producing circuitry and methods To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such paramete... | 12/07/2010 |
| 7840858 | Detection apparatus and test apparatus A detection apparatus is provided. The detection apparatus includes; a multi-strobe generating section that generates a plurality of strobe signals with phases different from one another; a plurality of acquiring sections each of which acquires a signal value of a s... | 11/23/2010 |
| 7805641 | Test apparatus for regulating a test signal supplied to a device under test and method thereof A test apparatus tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock si... | 09/28/2010 |
| RE41787 | Method and circuit for generating a tracking error signal using differential phase detection A circuit for generating tracking error signal using differential phase detection, comprising a quadrant photodetector for receiving optical signal and inducting splitting signal A, splitting signal B, splitting signal C and splitting signal D, two adders for genera... | 09/28/2010 |
| 7797589 | Detector for detecting information carried by a signal having a sawtooth-like shape A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a first band-pass filter with center frequency around a first frequency value for filtering the signal and generating a first filtered signal, a second band-... | 09/14/2010 |
| 7783935 | Bit error rate reduction buffer In a preferred embodiment, the invention provides a circuit for reducing bit error rates. A data recovery circuit recovers data from a first HSS link to differential bit pair inputs. Data from the differential bit pair outputs of the data recovery circuit drive diff... | 08/24/2010 |
| 7761748 | Methods and apparatus for managing clock skew between clock domain boundaries Methods and apparatus provide for: a plurality of stages of combinational logic, each stage including a full latch circuit operable to transfer data into the given stage of combinational logic and a transparent latch circuit operable transfer output data from the gi... | 07/20/2010 |
| 7761749 | Apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the... | 07/20/2010 |
| 7730366 | Phase error determination method and digital phase-locked loop system In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as ... | 06/01/2010 |
| 7725778 | Semiconductor integrated circuit and electronic device A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably s... | 05/25/2010 |
| 7702967 | Method for monitoring an internal control signal of a memory device and apparatus therefor Disclosed is a method for monitoring an internal control signal of a memory device and an apparatus therefore. The method includes (a) generating a first signal having a first pulse width by a burst operation command, (b) receiving the first signal, and generating N... | 04/20/2010 |
| 7681091 | Signal integrity measurement systems and methods using a predominantly digital time-base generator Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulat... | 03/16/2010 |
| 7681090 | Ripple correlation control based on limited sampling A method for controlling a variable of a switching electrical circuit detects values for each of a first waveform and of a second waveform in the switching circuit at a beginning of and at a predetermined instant during a switching interval of a switching operation ... | 03/16/2010 |
| 7647535 | Using a delay clock to optimize the timing margin of sequential logic A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register th... | 01/12/2010 |
| 7640461 | On-chip circuit for transition delay fault test pattern generation with launch off shift A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a la... | 12/29/2009 |
| 7634693 | Method and apparatus for analyzing serial data streams An apparatus and method for processing a data signal is provided. An acquisition unit of a test instrument acquires a data signal for a predetermined time. The data signal is stored in a memory of the test instrument and a clock recovery unit recovers a clock signal... | 12/15/2009 |
| 7627790 | Apparatus for jitter testing an IC An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between s... | 12/01/2009 |
| 7624310 | System and method for initializing a memory system, and memory device and processor-based system using same Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane ske... | 11/24/2009 |
| 7624311 | Method and apparatus for converting interface between high speed data having various capacities Provided are a method and an apparatus for converting an interface between high speed data having various capacities. The apparatus includes a data transmitting part and a data receiving part. The data transmitting part generates a deskew channel having respective t... | 11/24/2009 |
| 7620857 | Controllable delay device Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit output. Each delay element is an active circuit with a fixed transit time... | 11/17/2009 |
| 7600162 | Semiconductor device A semiconductor device including an interrupt pattern generator for generating an interrupt enabling signal and interrupt data, an input buffer for receiving input serial data, a selector, receiving through-data serially output from said input buffer and serial data... | 10/06/2009 |
| 7587640 | Method and apparatus for monitoring and compensating for skew on a high speed parallel bus Methods and apparatus are provided for monitoring and compensating for skew on a high speed parallel bus. Delay skew for a plurality of signals on a parallel bus is monitored by obtaining a plurality of samples of the plurality of signals for each unit interval; and... | 09/08/2009 |
| 7574632 | Strobe technique for time stamping a digital signal A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally incr... | 08/11/2009 |
| 7574633 | Test apparatus, adjustment method and recording medium There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing cloc... | 08/11/2009 |
