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| Number | Title | Issue Date |
| 8156385 | Systems and methods for backward-compatible constant-time exception-protection memory Embodiments of the invention provide a table-free technique for detecting all temporal and spatial memory access errors in programs supporting general pointers. Embodiments of the invention provide such error checking using constant-time operations. Embodiments of t... | 04/10/2012 |
| 8099636 | System and method for protecting memory stacks using a debug unit A method is disclosed for detecting a memory stack fault. The method may include reserving a memory stack for executing software instructions. The method may also include enabling a debug unit and as the software instructions are execute, utilizing the debug unit to... | 01/17/2012 |
| 8051337 | System and method for fast cache-hit detection A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a compari... | 11/01/2011 |
| 7895477 | Resilience to memory errors with firmware assistance Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having t... | 02/22/2011 |
| 7873879 | Mechanism to perform debugging of global shared memory (GSM) operations A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation tab... | 01/18/2011 |
| 7865784 | Write validation A write validation system that includes a first address signature collector module that generates a first address signature that is indicative of a write address of data when the data is received at a memory control module. A second address signature collector modul... | 01/04/2011 |
| 7818633 | Method and apparatus for identification of program check errors indicating code with high potential for storage overlay In a data processing system, in order to provide its operating system with a better mechanism to identify and track addressing errors with a high potential to cause a storage overlay, it is first determined whether or not, a program interrupt has occurred. It is nex... | 10/19/2010 |
| 7793165 | Selecting an address provider using a failover counter A method and system are provided to select address providers that provide mobile internet protocol devices with addresses for communication. An embodiment of the method includes obtaining an address request having a dynamic indicator and a failover counter. Upon obt... | 09/07/2010 |
| 7774658 | Method and apparatus to search for errors in a translation look-aside buffer A method and apparatus for discovering errors in a translation look-aside buffer (TLB). The TLB comprises a content addressable memory (CAM) and a random access memory (RAM). The TLB contains additional logic to check for error when the TLB is not in normal use to t... | 08/10/2010 |
| 7558990 | Semiconductor circuit device and method of detecting runaway In an embodiment of the invention, if a microprocessor detects runaway of a CPU executing a program, it starts a recovery program. The runaway in the program execution is detected by monitoring accesses a non-implementation space in a program space. If the CPU acces... | 07/07/2009 |
| 7421624 | Data recovery apparatus and method used for flash memory A data recovery apparatus and method used for a flash memory, which can recover data damaged or lost when power supplied to the flash memory is cut off while data operations are being consecutively performed on at least one data stored in the flash memory. The data ... | 09/02/2008 |
| 7418636 | Addressing error and address detection systems and methods Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether t... | 08/26/2008 |
| 7380179 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurali... | 05/27/2008 |
| 7370243 | Precise error handling in a fine grain multithreaded multicore processor A method and mechanism for error recovery in a processor. A multithreaded processor is configured to utilize software for hardware detected machine errors. Rather than correcting and clearing the detected errors, hardware is configured to report the errors precisely... | 05/06/2008 |
| 7366873 | Indirectly addressed vector load-operate-store method and apparatus A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 04/29/2008 |
| 7366829 | TLB tag parity checking without CAM read An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag ... | 04/29/2008 |
| 7363533 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit ser... | 04/22/2008 |
| 7356739 | System and program for controlling a distributed processing system The highly reliable distributed system is composed of a communication protocol processing unit which comprises a mailbox for storing a communication message, and executes communication protocol processing between data of an application program and a network controll... | 04/08/2008 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page int... | 03/04/2008 |
| 7340495 | Superior misaligned memory load and copy using merge hardware Method, apparatus, and program means for performing misaligned memory load and copy using aligned memory operations together with a SIMD merge instruction. The method of one embodiment comprises determining whether a memory operation involves a misaligned memory add... | 03/04/2008 |
| 7337352 | Cache entry error-connecting code (ECC) based at least on cache entry data and memory address Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry in... | 02/26/2008 |
| 7337372 | Method and apparatus for detecting multi-hit errors in a cache Multi-hit errors in a processor cache are detected by a multi-hit detection circuit coupled to the hit lines of the cache. The multi-hit detection circuit compares pairs of hit signals on the hit lines to determine if any two hit signals both indicate a hit. If mult... | 02/26/2008 |
| 7334159 | Self-testing RAM system and method A self-testing and correcting random access memory (RAM) device and methodology is disclosed herein. The device includes at least one array of memory to enable data storage and self-testing RAM interface for evaluating, correcting, and/or compensating for memory cel... | 02/19/2008 |
| 7328365 | System and method for providing error check and correction in memory systems A system for providing error check and correction (ECC) is provided. The system includes an ECC interface for storing ECC codes in a first memory system and storing data in a second memory system. The ECC interface corrects errors in the data received from the secon... | 02/05/2008 |
| 7325155 | Embedded system with reduced susceptibility to single event upset effects An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a ... | 01/29/2008 |
| 7293142 | Memory leak detection system and method using contingency analysis Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit contingency chains can be obtained. Analysis of these contingency chains ident... | 11/06/2007 |
| 7287102 | System and method for concatenating data A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start addresses of the first and second data segments. A read assembly module c... | 10/23/2007 |
| 7284107 | Special-use heaps Special purpose heaps are created to store different classes of data to which different rules apply. A library of functions is provided which is designed to respect the different classes of rules that apply to the different heaps, by storing data only on a heap that... | 10/16/2007 |
| 7281119 | Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and horizontal dependency between instructions, the horizontal dependency che... | 10/09/2007 |
| 7278014 | System and method for simulating hardware interrupts A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, call... | 10/02/2007 |
| 7272665 | Modular computer system and I/O module Without being restrained to a specific bus scheme, kinds of I/O modules connected to a processing module can be discriminated. Module exclusive selection parts respectively provided in I/O modules connected in a stacked form to a processing module via connectors jud... | 09/18/2007 |
| 7266811 | Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor Embodiments of systems, methods, and computer program products may facilitate translation of machine code associated with a first processor for execution on a second processor. Machine code associated with a first processor may be translated into a translated progra... | 09/04/2007 |
| 7260664 | Interrupt mechanism on an IO adapter that supports virtualization A mechanism for handling event notifications or interrupts in a logically partitioned computing system having IO adapters that support adapter virtualization are provided. A virtual adapter associated with a physical IO adapter detects an event, identifies a logical... | 08/21/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7251594 | Execution time modification of instruction emulation parameters To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as ... | 07/31/2007 |
| 7251755 | Apparatus and method for maintaining data integrity following parity error detection In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are s... | 07/31/2007 |
| 7246272 | Duplicate network address detection A plurality of data packets encoded according to a first protocol are received which encapsulate data encoded according to a second protocol. A first source address is extracted from the packets according to the first protocol, it is determined whether or not the fi... | 07/17/2007 |
| 7237085 | Architecture for a scalable heap analysis tool A method and software for analyzing a heap is described, in which a snapshot is made of a heap, which can be later analyzed by an analysis tool when a program that had run out of memory is no longer running. In one embodiment, an object allocated by the program is a... | 06/26/2007 |
| 7237092 | Microprocessor circuit for portable data carriers and method for operating the circuit A microprocessor circuit includes a control unit, a memory for free programming with at least one program having functions, a stack for buffer-storing data, a register bank having at least one register, and an auxiliary register that stores a number of bits, each of... | 06/26/2007 |
| 7231564 | Data block location verification An approach for performing data block location verification includes inserting an address value into a data block that identifies a desired location in nonvolatile memory for storing the data block. Prior to performing an operation that stores the data block to the ... | 06/12/2007 |
