Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 7853834 | Instruction-based timer control during debug A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the i... | 12/14/2010 |
| 7805640 | Use of submission data in hardware agnostic analysis of expected application performance Hardware independent performance metrics for application tasks are assembled and submitted to a central repository from multiple installations in the field. These metrics are requested by and provided to specific computing devices, and used to calculate expected per... | 09/28/2010 |
| 7797588 | Mechanism to provide software guaranteed reliability for GSM operations In a global shared memory (GSM) environment, an initiating task at a first node with a host fabric interface (HFI) uses epochs to provide reliability of transmission of packets via a network fabric to a target task. The HFI generates a packet for the initiating task... | 09/14/2010 |
| 7761747 | Interrupt control circuit An interrupt control circuit has a condition storage circuit for storing and outputting a reference time and an error detection circuit for outputting a signal indicating error detection when an interrupt request is not generated within a period from a predetermined... | 07/20/2010 |
| 7725777 | Identification of root cause for a transaction response time problem in a distributed environment Method and apparatus for identifying a cause for a response time problem for a transaction in a distributed computing system that includes a central server and a plurality of subsystems. Data is stored at each subsystem relating to sub-transactions of transactions p... | 05/25/2010 |
| 7721159 | Passing debug information A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains var... | 05/18/2010 |
| 7689874 | Data processing device and method for monitoring correct operation of a data processing device A method for monitoring the correct operations of a data processing device including changing a subsystem from an authorized state to an unauthorized state, executing the partial operating sequence, and resetting any subsystem state from the unauthorized state to th... | 03/30/2010 |
| 7574631 | Circuit arrangement and method for secure data processing Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has ... | 08/11/2009 |
| 7565581 | Error handling policy Described are techniques for use with an error handling policy for a data storage system. Error handling criteria may be specified for controlling behavior of the data storage system upon the occurrence of an internal processing error occurring when performing an an... | 07/21/2009 |
| 7543195 | Method and system for managing time-out events in a storage area network A method and system to enter a time out interval in a storage area network includes identifying a time slot in a sequence of time slots to insert a time out event for the event in the storage area network, determining if other events in the storage network already h... | 06/02/2009 |
| 7506217 | Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an en... | 03/17/2009 |
| 7496800 | Malfunction monitoring method and system In a method, an interrupt is generated to the processing unit every predetermined period. The predetermined period is shorter than a predetermined timeout period. A watchdog signal is changed in response to each of the generated interrupts. The interrupt generation ... | 02/24/2009 |
| 7487407 | Identification of root cause for a transaction response time problem in a distributed environment Method and apparatus for identifying a cause for a response time problem for a transaction in a distributed computing system that includes a central server and a plurality of subsystems. Data is stored at each subsystem relating to sub-transactions of transactions p... | 02/03/2009 |
| 7428674 | Monitoring the state vector of a test access port Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitor... | 09/23/2008 |
| 7406634 | Method and apparatus for utilizing an exception handler to avoid hanging up a CPU when a peripheral device does not respond A method and apparatus utilizes an exception handler to implement LOAD and STORE instructions for moving data between a peripheral device and CPU registers. TLB entries for peripheral devices are flagged invalid during initialization and an exception handler occurs ... | 07/29/2008 |
| 7386411 | Automatic hi-pot test apparatus and method An exemplary automatic hi-pot test apparatus (20) includes a high voltage supply (21), a transmission device configured for transmitting an electronic device (26) to be tested, a connecting device electrically connected to the high voltage suppl... | 06/10/2008 |
| 7383470 | Method, system, and apparatus for identifying unresponsive portions of a computer program A method, system, and apparatus are provided for identifying unresponsive portions of a computer program. According to the method, program code that can potentially result in unresponsive behavior is wrapped in timers. A timer is started on a background thread at th... | 06/03/2008 |
| 7383469 | Application management system and method An application management system and method is proposed. The application management system includes a first processor and a second processor. The first processor executes an application in a computer system. The second processor includes a monitor module to monitor ... | 06/03/2008 |
| 7373623 | Method and apparatus for locating circuit deviations A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by signal-flow graphs, the signal-flow graphs being composed of a multiplicity of... | 05/13/2008 |
| 7350098 | Detecting events of interest for managing components on a high availability framework Events of interest are detected in order to manage a high availability framework. In a framework in which a plurality of components are executing, the components are periodically polled to detect occurrence of the event of interest. A monitor is also established for... | 03/25/2008 |
| 7340575 | Method and a circuit for controlling access to the content of a memory integrated with a microprocessor A method and a circuit for controlling the access to all or part of the content of a memory that is integrated with a microprocessor, a priority-holding interrupt, at least one register of keys, and at least one access control algorithm contained in a second auxilia... | 03/04/2008 |
| 7340576 | Storage system with disk drive power-on-reset detection and recovery A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an A... | 03/04/2008 |
| 7337237 | Mechanism to provide callback capabilities for unreachable network clients A system and method for delivering asynchronous callbacks from a network server to clients that are unreachable by the network server. The system provides a callback server that receives callback registration requests from clients. The callback server generates a we... | 02/26/2008 |
| 7334167 | Circuit for detection of internal microprocessor watchdog device execution and method for resetting microprocessor system In a circuit for detection of internal microprocessor watchdog device execution comprising a microprocessor (6) with the internal watchdog device and with an input/output line (11) transmitting information about microprocessor reset, and a device for r... | 02/19/2008 |
| 7325171 | Measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subs... | 01/29/2008 |
| 7321214 | Motor control system A controller is operable in one of a plurality of operational modes, which include an estimated temperature computation performing mode for performing computing of an estimated temperature of the motor and an estimated temperature computation non-performing mode for... | 01/22/2008 |
| 7321213 | Motor controller A motor controller is provided with: an estimated temperature calculating means that calculates an estimated temperature of a motor; and a control unit that can perform a driving control of the motor only when the estimated temperature is not larger than a predeterm... | 01/22/2008 |
| 7320064 | Reconfigurable computing architecture for space applications A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port commu... | 01/15/2008 |
| 7315895 | Fault containment and error handling in a partitioned system with shared resources A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occu... | 01/01/2008 |
| 7310751 | Timeout event trigger generation A system is disclosed for generating a plurality of timeout event triggers in response to a plurality of kinds of timeout events. The system includes an overflow generator, which generates a plurality of overflow signals having a plurality of periods. The system als... | 12/18/2007 |
| 7299383 | Security method making deterministic real time execution of multitask applications of control and command type with error confinement The method is implemented with a management system of the time-triggered architecture type in association with a processor of a central processor unit that possesses a privileged execution mode to which access is protected by an instruction of the “call to system ... | 11/20/2007 |
| 7299437 | Method and apparatus for detecting timing exception path and computer product A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a mul... | 11/20/2007 |
| 7296186 | System-on-chip development apparatus for wire and wireless internet phone The present invention is directed to a system-on-chip development apparatus for wire/wireless Internet telephone. The system-on-chip development apparatus for wire/wireless Internet telephone according to the present invention adds functions indispensable to a RISC ... | 11/13/2007 |
| 7293198 | Techniques for maintaining operation of data storage system during a failure A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a c... | 11/06/2007 |
| 7287199 | Device capable of detecting BIOS status for clock setting and method thereof A method capable of detecting a status of a basic input/output system (BIOS) for setting a clock is applied to a clock generating device of a computer motherboard and sets the clock according to a signal status of the BIOS or a trigger signal. A device capable of de... | 10/23/2007 |
| 7284152 | Redundancy-based electronic device having certified and non-certified channels An at least dual-channel homogeneous-redundancy-based electronic device, preferably a dual-channel homogeneous-redundancy-based central processing unit of a stored-program control, that has at least one certified channel and at least one non-certified channel. The a... | 10/16/2007 |
| 7281040 | Diagnostic/remote monitoring by email A network device for use in a communication system having a technical support center operated by a technical support staff, the technical support center being in communication with the network device through a packet switching network. The network device includes on... | 10/09/2007 |
| 7272646 | Network monitor internals description A method and apparatus for a network monitor internals mechanism that serves to translate packet data into multiple concurrent streams of network event data is provided. The data translation is accomplished by interpreting both sides of each protocol transaction. | 09/18/2007 |
| 7251551 | On-vehicle electronic control device An on-vehicle electronic control device includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor including a nonvolatile program me... | 07/31/2007 |
| 7249270 | Method and apparatus for placing at least one processor into a power saving mode when another processor has access to a shared resource and exiting the power saving mode upon notification that the shared resource is no longer required by the other processor The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared res... | 07/24/2007 |
