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| Number | Title | Issue Date |
| 8145946 | Task execution apparatus, task execution method, and storage medium A task execution apparatus includes an execution unit configured to execute a task on a plurality of devices, an acquisition unit configured to acquire a cause of failure in execution by the execution unit, a confirmation unit configured to confirm that each device ... | 03/27/2012 |
| 8127177 | Apparatus and method for executing workflow If an error occurs during workflow processing, the present invention interrupts job processing appropriately while dispersing a load to the devices. When executing a plurality of processing steps with a plurality of devices in accordance with workflow setting inform... | 02/28/2012 |
| 8112662 | Portable electronic apparatus, processing apparatus for portable electronic apparatus, and data processing method in portable electronic apparatus A smart card comprises a storage unit in which various data are stored, a communication unit to perform data communication with an external apparatus, and a processing unit which executes processing corresponding to a command received via the communication unit. The... | 02/07/2012 |
| 8095825 | Error correction method with instruction level rollback This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed befo... | 01/10/2012 |
| 8090996 | Detecting soft errors via selective re-execution In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a... | 01/03/2012 |
| 7996716 | Containment and recovery of software exceptions in interacting, replicated-state-machine-based fault-tolerant components A method, system and article of manufacture are disclosed for error recovery in a replicated state machine. A batch of inputs is input to the machine, and the machine uses a multitude of components for processing those inputs. Also, during this processing, one of sa... | 08/09/2011 |
| 7921329 | Worker thread corruption detection and remediation A thread has a corruption detection mechanism that compares a beginning state of a function with an ending state to determine any inconsistencies. Based on the type of inconsistency, a remedial action may be taken, such as ignoring the inconsistency, cleaning up the... | 04/05/2011 |
| 7865771 | Command processing devices, command processing systems, and methods of processing a command A client device includes a command processing device. The command processing device is configured to transmit an error signal while in an abnormal operation mode to prevent an error due to no response to a command received from an external source and process the com... | 01/04/2011 |
| 7509531 | Data transmission ports with data-integrity transaction controlling unit and method for performing the same The present invention discloses re-configurable data transmission ports with data-integrity transaction controlling unit in a computerized computer and the method for performing the same. The controlling unit further includes a port-configuration detecting mechanism... | 03/24/2009 |
| 7430740 | Process group resource manager A process group resource manager for managing protected resources during transaction processing is disclosed. The process group resource manager comprises a first process configured to provide access to a protected resource during one or more transactions, the first... | 09/30/2008 |
| 7415633 | Method and apparatus for preventing and recovering from TLB corruption by soft error A detection and recovery mechanism is herein disclosed for soft errors corrupting TLB data. The mechanism works with a hardware page walker (HPW) and instruction steering control mechanisms in a processor to provide soft error recovery in the TLB arrays and latches.... | 08/19/2008 |
| 7383467 | Information processing apparatus having command-retry verification function, and command retry method A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. Wh... | 06/03/2008 |
| 7373549 | Error detection and recovery in a storage driver A command is received, at a network storage driver, from an operating system storage stack, wherein the command is for communication with a target storage device over a connection across a network. The command is selectively executed, a plurality of times over the c... | 05/13/2008 |
| 7356673 | System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of exe... | 04/08/2008 |
| 7340643 | Replay mechanism for correcting soft errors A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instruc... | 03/04/2008 |
| 7337444 | Method and apparatus for thread-safe handlers for checkpoints and restarts A method, apparatus, and computer instructions for executing a handler in a multi-threaded process handling a number of threads in a manner that avoids deadlocks. A value equal to the number of threads executing in the data processing system is set. The value is dec... | 02/26/2008 |
| 7331043 | Detecting and mitigating soft errors using duplicative instructions Software techniques are employed to mitigate soft errors. In particular, a compiler (or other executable code generator) may emit otherwise duplicative instructions targeting otherwise duplicative storage locations to facilitate run-time detection and, in some cases... | 02/12/2008 |
| 7328368 | Dynamic interconnect width reduction to improve interconnect availability In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector ... | 02/05/2008 |
| 7325155 | Embedded system with reduced susceptibility to single event upset effects An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a ... | 01/29/2008 |
| 7318169 | Fault tolerant computer A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long in... | 01/08/2008 |
| 7313727 | Adaptive recovery from system failure for application instances that govern message transactions Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its ow... | 12/25/2007 |
| 7302559 | Memory dump program boot method and mechanism, and computer-readable storage medium A memory dump program boot method includes the steps of defining, in non-volatile variables that are managed by a boot firmware of a computer system, boot information of a plurality of stand-alone dump programs that are installed in the computer system, and a table ... | 11/27/2007 |
| 7296142 | Multi-tiered retry scheme for reading copies of information from a storage medium Minimal and maximal numbers are established defining two levels of retry attempts to read system information from a storage medium. Multiple copies of the system information are stored on the storage medium. Attempts are made to successively read the copies until ei... | 11/13/2007 |
| 7278062 | Method and apparatus for responding to access errors in a data processing system In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to ... | 10/02/2007 |
| 7272748 | Method and apparatus to detect and recover from a stack frame corruption A prologue and an epilogue of a function are hooked. Completion of the prologue is stalled in a first state of a stack frame, and a copy of the first state of the stack frame is saved. Completion of the prologue is initiated, permitting execution of the function. Co... | 09/18/2007 |
| 7263631 | Soft error detection and recovery A logic circuit is provided that implements soft error detection and recovery for protecting the logic circuit from the negative effects of soft errors caused by single event upsets. The logic circuit may include a configurable processing module, an input buffer, an... | 08/28/2007 |
| 7260742 | SEU and SEFI fault tolerant computer A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run add... | 08/21/2007 |
| 7257730 | Method and apparatus for supporting legacy mode fail-over driver with iSCSI network entity including multiple redundant controllers The invention is directed to a method and apparatus for supporting legacy mode fail-over drivers with an iSCSI network entity including multiple redundant controllers. In an exemplary aspect of the present invention, to support legacy mode fail-over drivers with an ... | 08/14/2007 |
| 7237148 | Functional interrupt mitigation for fault tolerant computer A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or ci... | 06/26/2007 |
| 7231554 | Transparent consistent active replication of multithreaded application programs A method and system for transparent consistent active replication of multithreaded application programs is described. At each replica, control messages that contain mutex ordering information indicating the order in which threads in the replicas claim mutexes are mu... | 06/12/2007 |
| 7228459 | Apparatus and method that provides a primary server and a backup server that both support a RADIUS client and share an IP address A primary server and a backup server that both run a RADIUS client in a cold start configuration share a single IP address that includes a limited number of message identifiers (MIDs). The primary server and the backup server each have a small number of fixed messag... | 06/05/2007 |
| 7225383 | System and method for enhancing communication between devices in a computer system An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send... | 05/29/2007 |
| 7216252 | Method and apparatus for machine check abort handling in a multiprocessing system In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A ma... | 05/08/2007 |
| 7216255 | Adaptive recovery from system failure for application instances that govern message transactions Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its ow... | 05/08/2007 |
| 7213064 | Methods and systems for job-based accounting The present invention relates to an automated, mobile method for remotely managing the resources of a job-based business through real-time allocation of the resources among a set of user-defined virtual spending accounts. The method enables the user to establish two... | 05/01/2007 |
| 7199663 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 04/03/2007 |
| 7194671 | Mechanism handling race conditions in FRC-enabled processors An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit... | 03/20/2007 |
| 7181644 | Method for synchronizing data utilized in redundant, closed loop control systems A method for synchronizing data utilized in a redundant, closed-loop feedback control system is disclosed. In an exemplary embodiment, the method includes configuring a plurality of control nodes within the control system, with each of the plurality of control nodes... | 02/20/2007 |
| 7178011 | Predication instruction within a data processing system Within a data processing system, prediction instructions are provided which add conditional behaviour to associated program instructions. ... | 02/13/2007 |
| 7165186 | Selective checkpointing mechanism for application components A system and method for selectively checkpointing application components. In one embodiment this method may include deploying a plurality of application components on a server, determining checkpoint information for each application component on the server, and sele... | 01/16/2007 |
