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User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 8190935 | Information processing apparatus and method of controlling operating frequency of an information processing apparatus An information processing apparatus has a CPU, a clock supply unit configured to supply a clock signal, a CPU idle ratio obtaining unit configured to obtain the idle ratio of the CPU at each predetermined time, a clock control unit configured to determine an operati... | 05/29/2012 |
| 8185761 | “Subset PHY” approach for reducing power consumption during periods of low link utilization A system and method for reducing power consumption during periods of low link utilization. A single enhanced core can be defined that enables operation of subset of parent physical layer devices (PHYs). The subset and parent PHYs can have a fundamental relationship ... | 05/22/2012 |
| 8181049 | Method for controlling a frequency of a clock signal to control power consumption and a device having power consumption capabilities A method for controlling power consumption of a processor, the method includes: receiving an indicator that indicates that the processor is expected to change its activity; determining, in response to the indicator and to a current power consumption of the processor... | 05/15/2012 |
| 8176347 | Microprocessor that performs adaptive power throttling A microprocessor that performs adaptive power throttling includes a calculation unit configured to calculate an average power consumed by the microprocessor over a most recent predetermined sample time and to determine whether the average power is less than a predet... | 05/08/2012 |
| 8171320 | Information processing apparatus, operation control method and operation control program storage medium An information processing apparatus having a processing circuit to execute a program by operating at a set operating frequency, including: a measuring section that measures an elapsed time from the user's last operation; a notification section that notifies operatio... | 05/01/2012 |
| 8166322 | Portable terminal device A portable terminal device includes a supplying unit for supplying, to a CPR, an operating frequency of a clock signal used to operate the CPU, a setting unit for setting one clock level out of a plurality of clock levels assigned with the operating frequency in acc... | 04/24/2012 |
| 8166321 | Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determin... | 04/24/2012 |
| 8166323 | Thread migration to improve power efficiency in a parallel processing environment A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another... | 04/24/2012 |
| 8135970 | Microprocessor that performs adaptive power throttling A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined ma... | 03/13/2012 |
| 8127161 | Data processing apparatus An access stop control apparatus is provided in a resource control apparatus so that reception of access from a master apparatus is temporarily stopped during changing of a clock frequency and the clock frequency is changed at safe timing. Thereby, the operation of ... | 02/28/2012 |
| 8127162 | Apparatus, method, and computer program product for processing information which includes a power-saving mode having a plurality of sub power modes A receiving unit receives data from an external network device through a network. A determining unit determines whether a data processing is needed for the data received by the receiving unit. When the determining unit determines that the data processing is needed f... | 02/28/2012 |
| 8122270 | Voltage stabilization for clock signal frequency locking A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can ... | 02/21/2012 |
| 8117474 | CPU clock control during cache memory stall An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the pre... | 02/14/2012 |
| 8117473 | Noise reduction by returning to normal mode upon above threshold usage while periodically changing between sleep mode and low frequency mode A noise reduction apparatus and method of a processor to which a dynamic power management technique is applied. The noise reduction apparatus includes a mode setting unit for detecting a use state of a processor and setting an operation mode; and a power supply unit... | 02/14/2012 |
| 8095813 | Integrated circuit systems having processor-controlled clock signal generators therein that support efficient power management Exemplary embodiments of the invention provide a clock generation apparatus, system, and method, which include power management. The apparatus is couplable to second circuitry which has a clock input terminal and an inverted clock output terminal. An exemplary appar... | 01/10/2012 |
| 8086885 | Runtime control of system performance An apparatus includes a hardware unit having an interface to a clock generator, an interface to a power supply and an interface to a software unit. The interface to the software unit is configurable to receive a request from the software unit that identifies at leas... | 12/27/2011 |
| 8086884 | System and method for implementing an integrated circuit having dynamically variable power limit An integrated circuit having a dynamically variable power limit is provided. The integrated circuit comprises power management logic operable to receive notification of a dynamically set power limit value and operable to dynamically regulate the integrated circuit's... | 12/27/2011 |
| 8074093 | Method and system for optimizing the completion of computing operations Computer software that manages the amount of power provided to a processing unit for a specific process task, optimizing the processing speed of that specific task without overheating the processing unit. In the optimization method, the software initially counts the... | 12/06/2011 |
| 8065541 | Server power consumption controller, and method and computer program for controlling server power consumption A power consumption controller controls the power consumption of a physical server having a virtual server. A management server determines an unused CPU budget from the difference between the total amount of the loads of respective virtual servers and a hypervisor a... | 11/22/2011 |
| 8065542 | Distributed table-driven power mode computation for controlling optimal clock and voltage switching A method for computing the optimal power mode for a system-on-chip (SoC) in which both the clock and Vdd settings are controlled. Information from hardware blocks is synthesized into a global power mode for the entire SoC. The clocks can be disabled or enabled, and ... | 11/22/2011 |
| 8065543 | Method, system, and apparatus for dynamic clock adjustment A method, apparatus, article of manufacture, and system, the method including, in some embodiments, determining an impedance of a power distribution network of a load for a range of frequencies, and adjusting a functionality of the load based on a relationship betwe... | 11/22/2011 |
| 8060766 | Microprocessor performance and power optimization through inductive voltage droop monitoring and correction A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitori... | 11/15/2011 |
| 8060765 | Power estimation based on block activity A power monitor for electronic devices, such as computer chips, is used to estimate the power consumption and to compare the estimated power consumption against the power budget. The estimated power consumption is based on activity signals from various functional bl... | 11/15/2011 |
| 8046615 | Microcomputer system with reduced power consumption A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower fr... | 10/25/2011 |
| 8032772 | Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microproce... | 10/04/2011 |
| 8028183 | Power cap lower bound exploration in a server environment Disclosed is a computer implemented method, computer program product, and apparatus for determining a safe lower bound for a commonly powered data processing system. A power management module operates the data processing system using at least one nominal operating p... | 09/27/2011 |
| 8028182 | Dynamic CPU voltage regulator phase shedding A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a performance state, lookup voltage regulator information for new performa... | 09/27/2011 |
| 8020015 | Method and apparatus for on-demand power management An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing s... | 09/13/2011 |
| 8015423 | Temporally normalized processor utilization A temporally normalized processor utilization trace is generated. ... | 09/06/2011 |
| 7996695 | Circuits and methods for sleep state leakage current reduction A circuit for reducing sleep state current leakage is described. The circuit includes a hardware unit selected from at least one of a latch, a flip-flop, a comparator, a multiplexer, or an adder. The hardware unit includes a first node. The hardware unit further inc... | 08/09/2011 |
| 7975155 | Apparatus and method for controlling voltage and frequency A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one indication of a load of the system and to determine a voltage level and a clock signal ... | 07/05/2011 |
| 7962773 | Micro controller unit (MCU) with RTC A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processi... | 06/14/2011 |
| 7958483 | Clock throttling based on activity-level signals An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is configured to receive a clock signal from a clock signal generator. The clock signal to at least a portion of... | 06/07/2011 |
| 7941682 | Optimum power management of system on chip based on tiered states of operation Optimum power management of system on chip based on tiered states of operation is disclosed. In one embodiment, a system on chip includes a hardware module including one or more of a microcontroller, a microprocessor, a DSP core, a memory, a timing source, a periphe... | 05/10/2011 |
| 7930574 | Thread migration to improve power efficiency in a parallel processing environment A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another... | 04/19/2011 |
| 7925910 | Systems, methods and devices for limiting current consumption upon power-up Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage sig... | 04/12/2011 |
| 7917788 | SOC with low power and performance modes A system on a chip includes a processing module, ROM, RAM, and a clocking circuit. The clock circuit is coupled to produce a first clock signal when the SOC is in a low power mode and to produce a second clock signal when the SOC is in a performance mode, where the ... | 03/29/2011 |
| 7917789 | System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power/watt. In at least one embodiment, the present invention is intended to optimize proce... | 03/29/2011 |
| 7900071 | Apparatus and method to manage power in a computing device A method to manage power in a computing device comprising a controller assembly and a storage assembly comprising a plurality of data storage devices, by selecting a processor parameter, establishing a threshold processor parameter value, establishing a threshold ov... | 03/01/2011 |
| 7895457 | Memory card with power saving A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable si... | 02/22/2011 |
