Notes

(1) Note. Instruction data are defined in the glossary for this class to be data representative of an operation and identifying its operands, if any. (2) Note. Process and apparatus for processing instruction data that are classified herein are predicated on a particular, identifiable architecture of a computer or digital data processing system that directs the nature of the processing. Multiple computer and process coordinating (e.g., task management, task control) is classified elsewhere. See SEE OR SEARCH CLASS notes below. (3) Note. Register level transactions at the level of the arithmetic logic unit (ALU-level) or functional unit (FU-level) and logic for realizing such transactions are often a part of instruction processing, per se. General purpose, digital logic circuits, however, are classified elsewhere. See SEE OR SEARCH CLASS notes below. (4) Note. Exceptions, interrupts, and traps classified herein recite the details of the internal operation of the hardware or the microcode of the processor with only nominal recitation of the stimulus resulting in the exception, interrupt or trap. Process and apparatus for queuing or scheduling interrupts or signals in a computer or digital data processing system are classified elsewhere. See SEE OR SEARCH CLASS notes below. Process and apparatus directed to reliability and testing utilizing halts, interrupts, and traps are also classified elsewhere. See SEE OR SEARCH CLASS notes below. (5) Note. Virtual machine or virtual processor is classified elsewhere. See SEE OR SEARCH CLASS notes below. (6) Note. Process and apparatus for dynamically aligning instruction data are classified herein. Process and apparatus for shifting memory spaces, such as, boundary alignment related to memory addressing and page mapping are classified elsewhere. See SEE OR SEARCH CLASS notes below. Compilers performing static alignment are classified elsewhere. See SEE OR SEARCH CLASS notes below. Process and apparatus for aligning for data entry or compacting in cache memory typically are classified elsewhere. See SEE OR SEARCH CLASS notes below. (7) Note. Emulation for decoding instruction data for execution is classified herein; however, emulation of system component for compatibility is classified elsewhere. See SEE OR SEARCH CLASS notes below. Emulation directed to testing is also classified elsewhere. See SEE OR SEARCH CLASS notes below. (8) Note. Process and apparatus for locating and retrieving instruction data in direct support of an instruction pipeline are classified herein; however, process and apparatus for accessing and controlling memory at other higher levels (e.g., cache memory, disk memory, and shared memory) are classified elsewhere. See SEE OR SEARCH CLASS notes below. (9) Note. Process and apparatus nominally reciting addressing schemes and address data generation may be classified herein; however, process and apparatus for generalized address forming, addressing operands, generating addresses in response to microinstructions, and addressing in combination with particular memory systems are classified elsewhere. See SEE OR SEARCH CLASS notes below. (10) Note. Process and apparatus for decoding instruction data to determine their meaning for subsequent execution or decision making are classified herein; however, generic decoding circuits, methods, and programs are classified elsewhere. See SEE OR SEARCH CLASS notes below. (11) Note. Process and apparatus for issuing or dispatching of instruction data to hardware elements internal to a processor for decoding or executing are classified herein; however, process and apparatus for dispatching in the field of process control for task management dealing with process scheduling, load balancing, etc., are classified elsewhere. See SEE OR SEARCH CLASS notes below. (12) Note. Process and apparatus for dynamically controlling the issuance or execution of instruction data based on analysis of hardware-resource availability, hardware-resource utilization, and data dependency are classified herein; however, processes and apparatus for task resource management are classified elsewhere. See SEE OR SEARCH CLASS notes below. Dependency checking performed by a compiler is classified elsewhere. See SEE OR SEARCH CLASS notes below. Process and apparatus for enhancing the reliability and availability of functional units that include determining a fault condition are classified elsewhere. See SEE OR SEARCH CLASS notes below. (13) Note. Process and apparatus for dealing with resource management problems within a stream of instruction data, generally at the ALU/functional-unit level are classified herein; however, process and apparatus for resource management in a manufacturing environment are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (14) Note. Process and apparatus for reserving the use of functional units at the instruction level of a computer or digital data processing system are classified herein; however, processes and apparatus for reserving seats for travel, entertainment, etc. are classified elsewhere. See SEE OR SEARCH CLASS notes below. (15) Note. Process and apparatus utilizing hardware or microcode for processing and executing instruction data are classified herein; however, instruction processing being performed by a compiler, by an interpreter, or by an operating system is classified elsewhere. See SEE OR SEARCH CLASS notes below. Process and apparatus for high-level processing of input/output commands are classified elsewhere. See SEE OR SEARCH CLASS notes below. Process and apparatus for the sequencing common in computerized numerical controllers (CNC), industrial controllers, computer driven machining, etc., is classified elsewhere. See SEE OR SEARCH CLASS notes below. (16) Note. Hardwired sequencers are also often referred to as sequential state machines in the art. They are appropriately classified herein when they are performing control or sequencing of instruction data within a processor. (17) Note. Process and apparatus for graphic command processing are classified elsewhere. See SEE OR SEARCH CLASS notes below.