Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Number | Title | Issue Date |
| 7783860 | Load misaligned vector with permute and mask insert Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be... | 08/24/2010 |
| 7743231 | Fast sparse list walker Provided are a method, information processing system, and computer readable medium for identifying active bits in a vector. The method comprises receiving a pointer associated with a vector of bits. The pointer is associated with a current bit within the vector of b... | 06/22/2010 |
| 7404065 | Flow optimization and prediction for VSSE memory operations In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instructio... | 07/22/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7305487 | Optimized scalable network switch In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2m plu... | 12/04/2007 |
| 7275148 | Data processing system using multiple addressing modes for SIMD operations and method thereof Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/25/2007 |
| 7234022 | Cache accumulator memory for performing operations on block operands Various embodiments of systems and methods for performing accumulation operations on block operands are disclosed. In one embodiment, an apparatus may include a memory, a functional unit that performs an operation on block operands, and a cache accumulator. The cach... | 06/19/2007 |
| 7219212 | Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/15/2007 |
| 7174014 | Method and system for performing permutations with bit permutation instructions The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of... | 02/06/2007 |
| 7149875 | Data reordering processor and method for use in an active memory device An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses,... | 12/12/2006 |
| 7146515 | System and method for selectively executing a reboot request after a reset to power on state for a particular partition in a logically partitioned system A system, method, and computer program product are disclosed for executing a reliable warm reboot of one of multiple partitions included in a logically partitioned data processing system. The data processing system includes partition hardware. A request to reboot a ... | 12/05/2006 |
| 7140019 | Scheduler of program instructions for streaming vector processor having interconnected functional units A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the... | 11/21/2006 |
| 7120898 | Intermediate representation for multiple exception handling models As described herein, an intermediate representation of a source code file may be used to explicitly express exception handling control flow prior to generating object code for the source code. As further described herein, a single uniform set of instructions of the ... | 10/10/2006 |
| 7107258 | Search engine for large database search using CAM and hash A search engine having a controller, a memory, and at least one hash-CAM (H-CAM). The memory includes a database of search values and associate content or just associate content. The controller uses search values to access the memory to obtain the search results. Th... | 09/12/2006 |
| 7107436 | Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/12/2006 |
| 7100019 | Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as reg... | 08/29/2006 |
| 7069557 | Network processor which defines virtual paths without using logical path descriptors A virtual path feature in which several virtual channels share an assigned amount of bandwidth is implemented in a network processor. The network processor maintains a schedule indicative of respective times at which a plurality of virtual channels are to be service... | 06/27/2006 |
| 7043607 | Information processing system and cache flash control method used for the same The vector unit 21 outputs a first flash address to the flash address array 24. The vector unit 31 outputs a second flash address to the flash address array 34. In the master unit 2, the flash address array 24 compares an ad... | 05/09/2006 |
| 7028143 | Narrow/wide cache A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said fir... | 04/11/2006 |
| 7016984 | System controller using plural CPU's In a system controller in which a plurality of CPUs connected through a shared bus are connected to a plurality of memory units or IO devices through a bus for separate transfer of a read instruction from a read data return, a CPU which has issued a new instruction ... | 03/21/2006 |
| 7007138 | Apparatus, method, and computer program for resource request arbitration In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbi... | 02/28/2006 |
| 6963977 | Circuits and methods for modular exponentiation The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitionin... | 11/08/2005 |
| 6957324 | Computer system and method of controlling computation A vector computer system includes a plurality of memory banks 40, a vector processor 11, and a plurality of additional processing units 30 each of which is connected to one of the memory banks 40. Each of the additional processing units | 10/18/2005 |
| 6948112 | System and method for performing backward error recovery in a computer A system for performing data error recovery includes a memory unit and a memory controller. The memory unit includes a plurality of memory locations, and the memory controller maintains a checksum in one of the memory locations. At various times, the memory controll... | 09/20/2005 |
| 6938078 | Data processing apparatus and data processing method A data processing apparatus of the present invention includes a plurality of nodes each of which includes at least one processor and which is divided to a plurality groups, a bus to which the nodes are connected, and memory elements provided in the nodes, respective... | 08/30/2005 |
| 6865517 | Aggregation of sensory data for distributed decision-making A method, apparatus and computer product that enables a processor associated with a node in a computer system having various nodes, the nodes having sensors which provide data, and the nodes being connected by a communications facility acquiring local data from the ... | 03/08/2005 |
| 6816960 | Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution A vector artchitecture processing unit according to the present invention comprises a vector scatter (VSC) address coincidence detection unit 3 that comprises registers in which an area start address and an area end address of an area specified by an area-spe... | 11/09/2004 |
| 6813701 | Method and apparatus for transferring vector data between memory and a register file A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler identifies the use of vector data in an application program and implemen... | 11/02/2004 |
| 6742106 | Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst tra... | 05/25/2004 |
| 6665749 | Bus protocol for efficiently transferring vector data The present invention provides a bus architecture for a data processing system that improves transfers of vector data using a vector transfer unit (VTU). An external bus is coupled between the vector transfer unit and the memory. The external bus includes... | 12/16/2003 |
| 6625720 | System for posting vector synchronization instructions to vector instruction queue to separate vector instructions from different application programs A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector instructions are used for transferring the vector data between memory and registers used to perform calculations on the vector ... | 09/23/2003 |
| 6571386 | Apparatus and method for program optimizing An optimizer (100) comprises a memory (110) and a processor (130). The memory stores a program (200) to be optimized and optimization software (301). Controlled by the optimization software, the processor (120) (a) determines local vectors ("local") in in... | 05/27/2003 |
| 6513107 | Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing ... | 01/28/2003 |
| 6484220 | Transfer of data between processors in a multi-processor system A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location... | 11/19/2002 |
| 6336179 | Dynamic scheduling mechanism for an asynchronous/isochronous integrated circuit interconnect bus A first counter sequentially counts a plurality of numbers from respective sources requesting transfer of data. Each of the numbers represents an amount of isochronous data to transfer over the bus from the respective ones of the sources during a frame on... | 01/01/2002 |
| 6324611 | Physical layer interface and method for arbitration over serial bus using digital line state signals A physical layer interface for a serial bus includes a controller for producing parallel data representing a near-end line state of the serial bus. A line transmitter is connected to the controller for converting the parallel data therefrom into serial da... | 11/27/2001 |
| 6308250 | Method and apparatus for processing a set of data values with plural processing units mask bits generated by other processing units A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector of mask bits to generate an iota vector having a sequence... | 10/23/2001 |
| 6253304 | Collation of interrupt control devices A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second pr... | 06/26/2001 |
| 6202130 | Data processing system for processing vector data and method therefor A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches ... | 03/13/2001 |
| 6141673 | Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector regis... | 10/31/2000 |
